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Treat TS_ICVARC cache as separate from TS_IVC cache

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Jemma Issroff 2022-02-02 09:14:59 -05:00 • committed by Aaron Patterson
parent 7b77d46671
commit 2913a2f5cf
Notes: git 2022-02-03 02:21:10 +09:00
5 changed files with 15 additions and 4 deletions
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2
misc/lldb_disasm.py
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@ -27,6 +27,7 @@ class IseqDisassembler:
TS_CDHASH = b'H'[0]
TS_IC = b'K'[0]
TS_IVC = b'A'[0]
TS_ICVARC = b'J'[0]
TS_ID = b'I'[0]
TS_ISE = b'T'[0]
TS_ISEQ = b'S'[0]
@ -48,6 +49,7 @@ class IseqDisassembler:
TS_ISE: "(iseq_inline_storage_entry *)%0#x",
TS_ID: "ID: %0#x",
TS_IVC: "(struct iseq_inline_iv_cache_entry *)%0#x",
TS_ICVARC: "(struct iseq_inline_cvar_cache_entry *)%0#x",
TS_IC: "(struct iseq_inline_cache_entry *)%0#x",
TS_CDHASH: "CDHASH (VALUE)%0#x",
TS_CALLDATA: "(struct rb_call_data *)%0#x",