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Change register definitions to match the entry point calling convention

The JIT entry point passes the CFP as RSI and the EC as RDI.  Lets match
that so we don't have to shuffle registers around.
This commit is contained in:
Aaron Patterson 2021-07-15 13:35:19 -07:00 committed by Alan Wu
parent 2a59bd7312
commit 84a1e04e58
2 changed files with 2 additions and 9 deletions

View file

@ -365,13 +365,6 @@ yjit_entry_prologue(const rb_iseq_t *iseq)
uint8_t *code_ptr = cb_get_ptr(cb, cb->write_pos);
ADD_COMMENT(cb, "yjit prolog");
// Fix registers for YJIT. The MJIT callback puts the ec in RDI
// and the CFP in RSI, but REG_CFP == RDI and REG_EC == RSI
mov(cb, REG0, RDI); // EC
mov(cb, REG1, RSI); // CFP
mov(cb, REG_EC, REG0);
mov(cb, REG_CFP, REG1);
// Load the current SP from the CFP into REG_SP
mov(cb, REG_SP, member_opnd(REG_CFP, rb_control_frame_t, sp));

View file

@ -5,8 +5,8 @@
#include "yjit_asm.h"
// Register YJIT receives the CFP and EC into
#define REG_CFP RDI
#define REG_EC RSI
#define REG_CFP RSI
#define REG_EC RDI
// Register YJIT loads the SP into
#define REG_SP RDX