mirror of
https://github.com/ruby/ruby.git
synced 2022-11-09 12:17:21 -05:00
Make op_ext an optional for code clarity (#6542)
This commit is contained in:
Jimmy Miller
GitHub
parent
e5058b58c2
commit
93a87f4963
Notes:
git
2022-10-14 07:17:37 +09:00
Merged-By: maximecb <maximecb@ruby-lang.org>
1 changed files with 50 additions and 42 deletions
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@ -161,6 +161,14 @@ impl X86Opnd {
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_ => unreachable!()
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}
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}
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pub fn is_some(&self) -> bool {
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match self {
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X86Opnd::None => false,
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_ => true
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}
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}
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}
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// Instruction pointer
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@ -382,7 +390,7 @@ fn write_opcode(cb: &mut CodeBlock, opcode: u8, reg: X86Reg) {
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}
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/// Encode an RM instruction
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fn write_rm(cb: &mut CodeBlock, sz_pref: bool, rex_w: bool, r_opnd: X86Opnd, rm_opnd: X86Opnd, op_ext: u8, bytes: &[u8]) {
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fn write_rm(cb: &mut CodeBlock, sz_pref: bool, rex_w: bool, r_opnd: X86Opnd, rm_opnd: X86Opnd, op_ext: Option<u8>, bytes: &[u8]) {
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let op_len = bytes.len();
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assert!(op_len > 0 && op_len <= 3);
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assert!(matches!(r_opnd, X86Opnd::Reg(_) | X86Opnd::None), "Can only encode an RM instruction with a register or a none");
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@ -439,7 +447,7 @@ fn write_rm(cb: &mut CodeBlock, sz_pref: bool, rex_w: bool, r_opnd: X86Opnd, rm_
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// MODRM.rm (3 bits)
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assert!(
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!(op_ext != 0xff && !matches!(r_opnd, X86Opnd::None)),
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!(op_ext.is_some() && r_opnd.is_some()),
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"opcode extension and register operand present"
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);
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@ -460,8 +468,8 @@ fn write_rm(cb: &mut CodeBlock, sz_pref: bool, rex_w: bool, r_opnd: X86Opnd, rm_
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// Encode the reg field
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let reg: u8;
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if op_ext != 0xff {
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reg = op_ext;
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if let Some(val) = op_ext {
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reg = val;
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} else {
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reg = match r_opnd {
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X86Opnd::Reg(reg) => reg.reg_no & 7,
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@ -522,7 +530,7 @@ fn write_rm(cb: &mut CodeBlock, sz_pref: bool, rex_w: bool, r_opnd: X86Opnd, rm_
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}
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// Encode a mul-like single-operand RM instruction
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fn write_rm_unary(cb: &mut CodeBlock, op_mem_reg_8: u8, op_mem_reg_pref: u8, op_ext: u8, opnd: X86Opnd) {
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fn write_rm_unary(cb: &mut CodeBlock, op_mem_reg_8: u8, op_mem_reg_pref: u8, op_ext: Option<u8>, opnd: X86Opnd) {
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assert!(matches!(opnd, X86Opnd::Reg(_) | X86Opnd::Mem(_)));
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let opnd_size = opnd.num_bits();
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@ -538,7 +546,7 @@ fn write_rm_unary(cb: &mut CodeBlock, op_mem_reg_8: u8, op_mem_reg_pref: u8, op_
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}
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// Encode an add-like RM instruction with multiple possible encodings
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fn write_rm_multi(cb: &mut CodeBlock, op_mem_reg8: u8, op_mem_reg_pref: u8, op_reg_mem8: u8, op_reg_mem_pref: u8, op_mem_imm8: u8, op_mem_imm_sml: u8, op_mem_imm_lrg: u8, op_ext_imm: u8, opnd0: X86Opnd, opnd1: X86Opnd) {
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fn write_rm_multi(cb: &mut CodeBlock, op_mem_reg8: u8, op_mem_reg_pref: u8, op_reg_mem8: u8, op_reg_mem_pref: u8, op_mem_imm8: u8, op_mem_imm_sml: u8, op_mem_imm_lrg: u8, op_ext_imm: Option<u8>, opnd0: X86Opnd, opnd1: X86Opnd) {
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assert!(matches!(opnd0, X86Opnd::Reg(_) | X86Opnd::Mem(_)));
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// Check the size of opnd0
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@ -561,17 +569,17 @@ fn write_rm_multi(cb: &mut CodeBlock, op_mem_reg8: u8, op_mem_reg_pref: u8, op_r
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// R/M + Reg
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(X86Opnd::Mem(_), X86Opnd::Reg(_)) | (X86Opnd::Reg(_), X86Opnd::Reg(_)) => {
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if opnd_size == 8 {
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write_rm(cb, false, false, opnd1, opnd0, 0xff, &[op_mem_reg8]);
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write_rm(cb, false, false, opnd1, opnd0, None, &[op_mem_reg8]);
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} else {
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write_rm(cb, sz_pref, rex_w, opnd1, opnd0, 0xff, &[op_mem_reg_pref]);
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write_rm(cb, sz_pref, rex_w, opnd1, opnd0, None, &[op_mem_reg_pref]);
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}
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},
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// Reg + R/M/IPRel
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(X86Opnd::Reg(_), X86Opnd::Mem(_) | X86Opnd::IPRel(_)) => {
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if opnd_size == 8 {
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write_rm(cb, false, false, opnd0, opnd1, 0xff, &[op_reg_mem8]);
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write_rm(cb, false, false, opnd0, opnd1, None, &[op_reg_mem8]);
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} else {
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write_rm(cb, sz_pref, rex_w, opnd0, opnd1, 0xff, &[op_reg_mem_pref]);
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write_rm(cb, sz_pref, rex_w, opnd0, opnd1, None, &[op_reg_mem_pref]);
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}
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},
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// R/M + Imm
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@ -640,7 +648,7 @@ pub fn add(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0x80, // opMemImm8
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0x83, // opMemImmSml
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0x81, // opMemImmLrg
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0x00, // opExtImm
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Some(0x00), // opExtImm
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opnd0,
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opnd1
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);
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@ -657,7 +665,7 @@ pub fn and(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0x80, // opMemImm8
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0x83, // opMemImmSml
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0x81, // opMemImmLrg
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0x04, // opExtImm
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Some(0x04), // opExtImm
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opnd0,
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opnd1
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);
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@ -705,7 +713,7 @@ pub fn call_label(cb: &mut CodeBlock, label_idx: usize) {
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/// call - Indirect call with an R/M operand
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pub fn call(cb: &mut CodeBlock, opnd: X86Opnd) {
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write_rm(cb, false, false, X86Opnd::None, opnd, 2, &[0xff]);
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write_rm(cb, false, false, X86Opnd::None, opnd, Some(2), &[0xff]);
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}
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/// Encode a conditional move instruction
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@ -721,7 +729,7 @@ fn write_cmov(cb: &mut CodeBlock, opcode1: u8, dst: X86Opnd, src: X86Opnd) {
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let sz_pref = reg.num_bits == 16;
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let rex_w = reg.num_bits == 64;
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write_rm(cb, sz_pref, rex_w, dst, src, 0xff, &[0x0f, opcode1]);
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write_rm(cb, sz_pref, rex_w, dst, src, None, &[0x0f, opcode1]);
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} else {
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unreachable!()
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}
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@ -770,7 +778,7 @@ pub fn cmp(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0x80, // opMemImm8
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0x83, // opMemImmSml
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0x81, // opMemImmLrg
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0x07, // opExtImm
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Some(0x07), // opExtImm
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opnd0,
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opnd1
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);
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@ -900,7 +908,7 @@ pub fn jmp_ptr (cb: &mut CodeBlock, ptr: CodePtr) { write_jcc_ptr(cb, 0xFF, 0xE9
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/// jmp - Indirect jump near to an R/M operand.
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pub fn jmp_rm(cb: &mut CodeBlock, opnd: X86Opnd) {
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write_rm(cb, false, false, X86Opnd::None, opnd, 4, &[0xff]);
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write_rm(cb, false, false, X86Opnd::None, opnd, Some(4), &[0xff]);
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}
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// jmp - Jump with relative 32-bit offset
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@ -913,7 +921,7 @@ pub fn jmp32(cb: &mut CodeBlock, offset: i32) {
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pub fn lea(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
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if let X86Opnd::Reg(reg) = dst {
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assert!(reg.num_bits == 64);
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write_rm(cb, false, true, dst, src, 0xff, &[0x8d]);
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write_rm(cb, false, true, dst, src, None, &[0x8d]);
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} else {
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unreachable!();
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}
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@ -981,9 +989,9 @@ pub fn mov(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
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assert!(imm.num_bits <= mem.num_bits);
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if mem.num_bits == 8 {
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write_rm(cb, false, false, X86Opnd::None, dst, 0xff, &[0xc6]);
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write_rm(cb, false, false, X86Opnd::None, dst, None, &[0xc6]);
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} else {
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write_rm(cb, mem.num_bits == 16, mem.num_bits == 64, X86Opnd::None, dst, 0, &[0xc7]);
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write_rm(cb, mem.num_bits == 16, mem.num_bits == 64, X86Opnd::None, dst, Some(0), &[0xc7]);
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}
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let output_num_bits:u32 = if mem.num_bits > 32 { 32 } else { mem.num_bits.into() };
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@ -995,10 +1003,10 @@ pub fn mov(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
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assert!(uimm.num_bits <= mem.num_bits);
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if mem.num_bits == 8 {
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write_rm(cb, false, false, X86Opnd::None, dst, 0xff, &[0xc6]);
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write_rm(cb, false, false, X86Opnd::None, dst, None, &[0xc6]);
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}
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else {
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write_rm(cb, mem.num_bits == 16, mem.num_bits == 64, X86Opnd::None, dst, 0, &[0xc7]);
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write_rm(cb, mem.num_bits == 16, mem.num_bits == 64, X86Opnd::None, dst, Some(0), &[0xc7]);
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}
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let output_num_bits = if mem.num_bits > 32 { 32 } else { mem.num_bits.into() };
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@ -1018,7 +1026,7 @@ pub fn mov(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
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0xC6, // opMemImm8
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0xFF, // opMemImmSml (not available)
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0xFF, // opMemImmLrg
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0xFF, // opExtImm
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None, // opExtImm
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dst,
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src
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);
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@ -1036,9 +1044,9 @@ pub fn movsx(cb: &mut CodeBlock, dst: X86Opnd, src: X86Opnd) {
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assert!(src_num_bits < dst_num_bits);
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match src_num_bits {
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8 => write_rm(cb, dst_num_bits == 16, dst_num_bits == 64, dst, src, 0xff, &[0x0f, 0xbe]),
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16 => write_rm(cb, dst_num_bits == 16, dst_num_bits == 64, dst, src, 0xff, &[0x0f, 0xbf]),
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32 => write_rm(cb, false, true, dst, src, 0xff, &[0x63]),
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8 => write_rm(cb, dst_num_bits == 16, dst_num_bits == 64, dst, src, None, &[0x0f, 0xbe]),
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16 => write_rm(cb, dst_num_bits == 16, dst_num_bits == 64, dst, src, None, &[0x0f, 0xbf]),
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32 => write_rm(cb, false, true, dst, src, None, &[0x63]),
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_ => unreachable!()
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};
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} else {
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@ -1116,7 +1124,7 @@ pub fn not(cb: &mut CodeBlock, opnd: X86Opnd) {
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cb,
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0xf6, // opMemReg8
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0xf7, // opMemRegPref
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0x02, // opExt
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Some(0x02), // opExt
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opnd
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);
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}
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@ -1132,7 +1140,7 @@ pub fn or(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0x80, // opMemImm8
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0x83, // opMemImmSml
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0x81, // opMemImmLrg
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0x01, // opExtImm
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Some(0x01), // opExtImm
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opnd0,
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opnd1
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);
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@ -1152,7 +1160,7 @@ pub fn pop(cb: &mut CodeBlock, opnd: X86Opnd) {
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X86Opnd::Mem(mem) => {
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assert!(mem.num_bits == 64);
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write_rm(cb, false, false, X86Opnd::None, opnd, 0, &[0x8f]);
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write_rm(cb, false, false, X86Opnd::None, opnd, Some(0), &[0x8f]);
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},
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_ => unreachable!()
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};
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@ -1174,7 +1182,7 @@ pub fn push(cb: &mut CodeBlock, opnd: X86Opnd) {
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write_opcode(cb, 0x50, reg);
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},
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X86Opnd::Mem(_mem) => {
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write_rm(cb, false, false, X86Opnd::None, opnd, 6, &[0xff]);
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write_rm(cb, false, false, X86Opnd::None, opnd, Some(6), &[0xff]);
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},
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_ => unreachable!()
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}
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@ -1191,7 +1199,7 @@ pub fn ret(cb: &mut CodeBlock) {
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}
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// Encode a single-operand shift instruction
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fn write_shift(cb: &mut CodeBlock, op_mem_one_pref: u8, _op_mem_cl_pref: u8, op_mem_imm_pref: u8, op_ext: u8, opnd0: X86Opnd, opnd1: X86Opnd) {
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fn write_shift(cb: &mut CodeBlock, op_mem_one_pref: u8, _op_mem_cl_pref: u8, op_mem_imm_pref: u8, op_ext: Option<u8>, opnd0: X86Opnd, opnd1: X86Opnd) {
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assert!(matches!(opnd0, X86Opnd::Reg(_) | X86Opnd::Mem(_)));
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// Check the size of opnd0
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@ -1221,7 +1229,7 @@ pub fn sal(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0xD1, // opMemOnePref,
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0xD3, // opMemClPref,
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0xC1, // opMemImmPref,
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0x04,
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Some(0x04),
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opnd0,
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opnd1
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);
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@ -1234,7 +1242,7 @@ pub fn sar(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0xD1, // opMemOnePref,
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0xD3, // opMemClPref,
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0xC1, // opMemImmPref,
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0x07,
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Some(0x07),
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opnd0,
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opnd1
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);
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@ -1247,7 +1255,7 @@ pub fn shl(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0xD1, // opMemOnePref,
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0xD3, // opMemClPref,
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0xC1, // opMemImmPref,
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0x04,
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Some(0x04),
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opnd0,
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opnd1
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);
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@ -1260,7 +1268,7 @@ pub fn shr(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0xD1, // opMemOnePref,
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0xD3, // opMemClPref,
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0xC1, // opMemImmPref,
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0x05,
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Some(0x05),
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opnd0,
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opnd1
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);
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@ -1277,7 +1285,7 @@ pub fn sub(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
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0x80, // opMemImm8
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0x83, // opMemImmSml
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0x81, // opMemImmLrg
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0x05, // opExtImm
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Some(0x05), // opExtImm
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opnd0,
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opnd1
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);
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@ -1314,10 +1322,10 @@ pub fn test(cb: &mut CodeBlock, rm_opnd: X86Opnd, test_opnd: X86Opnd) {
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let rm_resized = resize_opnd(rm_opnd, uimm.num_bits);
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if uimm.num_bits == 8 {
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write_rm(cb, false, false, X86Opnd::None, rm_resized, 0x00, &[0xf6]);
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write_rm(cb, false, false, X86Opnd::None, rm_resized, Some(0x00), &[0xf6]);
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cb.write_int(uimm.value, uimm.num_bits.into());
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} else {
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write_rm(cb, uimm.num_bits == 16, false, X86Opnd::None, rm_resized, 0x00, &[0xf7]);
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write_rm(cb, uimm.num_bits == 16, false, X86Opnd::None, rm_resized, Some(0x00), &[0xf7]);
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cb.write_int(uimm.value, uimm.num_bits.into());
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}
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},
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@ -1326,16 +1334,16 @@ pub fn test(cb: &mut CodeBlock, rm_opnd: X86Opnd, test_opnd: X86Opnd) {
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assert!(imm.num_bits <= 32);
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assert!(rm_num_bits == 64);
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write_rm(cb, false, true, X86Opnd::None, rm_opnd, 0x00, &[0xf7]);
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write_rm(cb, false, true, X86Opnd::None, rm_opnd, Some(0x00), &[0xf7]);
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cb.write_int(imm.value as u64, 32);
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},
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X86Opnd::Reg(reg) => {
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assert!(reg.num_bits == rm_num_bits);
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if rm_num_bits == 8 {
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write_rm(cb, false, false, test_opnd, rm_opnd, 0xff, &[0x84]);
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write_rm(cb, false, false, test_opnd, rm_opnd, None, &[0x84]);
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} else {
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write_rm(cb, rm_num_bits == 16, rm_num_bits == 64, test_opnd, rm_opnd, 0xff, &[0x85]);
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write_rm(cb, rm_num_bits == 16, rm_num_bits == 64, test_opnd, rm_opnd, None, &[0x85]);
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}
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},
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_ => unreachable!()
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@ -1361,7 +1369,7 @@ pub fn xchg(cb: &mut CodeBlock, rm_opnd: X86Opnd, r_opnd: X86Opnd) {
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// Write the opcode and register number
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cb.write_byte(0x90 + (r_reg.reg_no & 7));
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} else {
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write_rm(cb, false, true, r_opnd, rm_opnd, 0xff, &[0x87]);
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write_rm(cb, false, true, r_opnd, rm_opnd, None, &[0x87]);
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}
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} else {
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unreachable!();
|
||||
|
|
@ -1379,7 +1387,7 @@ pub fn xor(cb: &mut CodeBlock, opnd0: X86Opnd, opnd1: X86Opnd) {
|
|||
0x80, // opMemImm8
|
||||
0x83, // opMemImmSml
|
||||
0x81, // opMemImmLrg
|
||||
0x06, // opExtImm
|
||||
Some(0x06), // opExtImm
|
||||
opnd0,
|
||||
opnd1
|
||||
);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue