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https://github.com/ruby/ruby.git
synced 2022-11-09 12:17:21 -05:00
Allow comparing against 64-bit immediates on x86 (#6314)
This commit is contained in:
Kevin Newton
GitHub
parent
fc2d9fedc2
commit
9b48edd932
Notes:
git
2022-09-02 11:14:54 +09:00
Merged-By: maximecb <maximecb@ruby-lang.org>
1 changed files with 215 additions and 51 deletions
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@ -103,42 +103,6 @@ impl Assembler
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/// Split IR instructions for the x86 platform
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fn x86_split(mut self) -> Assembler
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{
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fn split_arithmetic_opnds(asm: &mut Assembler, live_ranges: &Vec<usize>, index: usize, unmapped_opnds: &Vec<Opnd>, left: &Opnd, right: &Opnd) -> (Opnd, Opnd) {
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match (unmapped_opnds[0], unmapped_opnds[1]) {
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(Opnd::Mem(_), Opnd::Mem(_)) => {
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(asm.load(*left), asm.load(*right))
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},
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(Opnd::Mem(_), Opnd::UImm(value)) => {
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// 32-bit values will be sign-extended
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if imm_num_bits(value as i64) > 32 {
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(asm.load(*left), asm.load(*right))
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} else {
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(asm.load(*left), *right)
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}
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},
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(Opnd::Mem(_), Opnd::Imm(value)) => {
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if imm_num_bits(value) > 32 {
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(asm.load(*left), asm.load(*right))
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} else {
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(asm.load(*left), *right)
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}
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},
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// Instruction output whose live range spans beyond this instruction
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(Opnd::InsnOut { idx, .. }, _) => {
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if live_ranges[idx] > index {
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(asm.load(*left), *right)
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} else {
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(*left, *right)
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}
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},
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// We have to load memory operands to avoid corrupting them
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(Opnd::Mem(_) | Opnd::Reg(_), _) => {
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(asm.load(*left), *right)
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},
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_ => (*left, *right)
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}
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}
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let live_ranges: Vec<usize> = take(&mut self.live_ranges);
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let mut asm = Assembler::new_with_label_names(take(&mut self.label_names));
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let mut iterator = self.into_draining_iter();
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@ -194,20 +158,36 @@ impl Assembler
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Insn::And { left, right, out } |
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Insn::Or { left, right, out } |
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Insn::Xor { left, right, out } => {
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let (split_left, split_right) = split_arithmetic_opnds(&mut asm, &live_ranges, index, &unmapped_opnds, left, right);
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match (unmapped_opnds[0], unmapped_opnds[1]) {
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(Opnd::Mem(_), Opnd::Mem(_)) => {
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*left = asm.load(*left);
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*right = asm.load(*right);
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},
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(Opnd::Mem(_), Opnd::UImm(_) | Opnd::Imm(_)) => {
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*left = asm.load(*left);
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},
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// Instruction output whose live range spans beyond this instruction
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(Opnd::InsnOut { idx, .. }, _) => {
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if live_ranges[idx] > index {
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*left = asm.load(*left);
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}
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},
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// We have to load memory operands to avoid corrupting them
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(Opnd::Mem(_) | Opnd::Reg(_), _) => {
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*left = asm.load(*left);
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},
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_ => {}
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};
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*left = split_left;
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*right = split_right;
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*out = asm.next_opnd_out(Opnd::match_num_bits(&[*left, *right]));
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asm.push_insn(insn);
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},
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Insn::Cmp { left, right } |
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Insn::Test { left, right } => {
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let (split_left, split_right) = split_arithmetic_opnds(&mut asm, &live_ranges, index, &unmapped_opnds, left, right);
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*left = split_left;
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*right = split_right;
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if let (Opnd::Mem(_), Opnd::Mem(_)) = (&left, &right) {
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let loaded = asm.load(*right);
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*right = loaded;
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}
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asm.push_insn(insn);
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},
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@ -329,6 +309,34 @@ impl Assembler
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/// Emit platform-specific machine code
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pub fn x86_emit(&mut self, cb: &mut CodeBlock) -> Vec<u32>
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{
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/// For some instructions, we want to be able to lower a 64-bit operand
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/// without requiring more registers to be available in the register
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/// allocator. So we just use the SCRATCH0 register temporarily to hold
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/// the value before we immediately use it.
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fn emit_64bit_immediate(cb: &mut CodeBlock, opnd: &Opnd) -> X86Opnd {
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match opnd {
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Opnd::Imm(value) => {
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// 32-bit values will be sign-extended
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if imm_num_bits(*value) > 32 {
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mov(cb, Assembler::SCRATCH0, opnd.into());
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Assembler::SCRATCH0
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} else {
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opnd.into()
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}
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},
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Opnd::UImm(value) => {
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// 32-bit values will be sign-extended
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if imm_num_bits(*value as i64) > 32 {
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mov(cb, Assembler::SCRATCH0, opnd.into());
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Assembler::SCRATCH0
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} else {
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opnd.into()
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}
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},
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_ => opnd.into()
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}
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}
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//dbg!(&self.insns);
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// List of GC offsets
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@ -365,26 +373,31 @@ impl Assembler
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},
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Insn::Add { left, right, .. } => {
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add(cb, left.into(), right.into())
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let opnd1 = emit_64bit_immediate(cb, right);
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add(cb, left.into(), opnd1);
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},
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Insn::FrameSetup => {},
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Insn::FrameTeardown => {},
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Insn::Sub { left, right, .. } => {
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sub(cb, left.into(), right.into())
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let opnd1 = emit_64bit_immediate(cb, right);
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sub(cb, left.into(), opnd1);
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},
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Insn::And { left, right, .. } => {
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and(cb, left.into(), right.into())
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let opnd1 = emit_64bit_immediate(cb, right);
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and(cb, left.into(), opnd1);
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},
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Insn::Or { left, right, .. } => {
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or(cb, left.into(), right.into());
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let opnd1 = emit_64bit_immediate(cb, right);
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or(cb, left.into(), opnd1);
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},
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Insn::Xor { left, right, .. } => {
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xor(cb, left.into(), right.into());
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let opnd1 = emit_64bit_immediate(cb, right);
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xor(cb, left.into(), opnd1);
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},
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Insn::Not { opnd, .. } => {
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@ -501,12 +514,14 @@ impl Assembler
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// Compare
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Insn::Cmp { left, right } => {
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cmp(cb, left.into(), right.into());
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let emitted = emit_64bit_immediate(cb, right);
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cmp(cb, left.into(), emitted);
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}
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// Test and set flags
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Insn::Test { left, right } => {
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test(cb, left.into(), right.into());
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let emitted = emit_64bit_immediate(cb, right);
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test(cb, left.into(), emitted);
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}
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Insn::JmpOpnd(opnd) => {
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@ -660,3 +675,152 @@ impl Assembler
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gc_offsets
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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fn setup_asm() -> (Assembler, CodeBlock) {
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(Assembler::new(), CodeBlock::new_dummy(1024))
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}
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#[test]
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fn test_emit_add_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.add(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c04881c0ff000000");
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}
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#[test]
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fn test_emit_add_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.add(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c049bbffffffffffff00004c01d8");
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}
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#[test]
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fn test_emit_and_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.and(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c04881e0ff000000");
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}
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#[test]
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fn test_emit_and_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.and(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c049bbffffffffffff00004c21d8");
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}
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#[test]
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fn test_emit_cmp_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.cmp(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 0);
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assert_eq!(format!("{:x}", cb), "4881f8ff000000");
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}
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#[test]
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fn test_emit_cmp_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.cmp(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 0);
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assert_eq!(format!("{:x}", cb), "49bbffffffffffff00004c39d8");
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}
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#[test]
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fn test_emit_or_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.or(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c04881c8ff000000");
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}
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#[test]
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fn test_emit_or_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.or(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c049bbffffffffffff00004c09d8");
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}
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#[test]
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fn test_emit_sub_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.sub(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c04881e8ff000000");
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}
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#[test]
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fn test_emit_sub_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.sub(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c049bbffffffffffff00004c29d8");
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}
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#[test]
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fn test_emit_test_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.test(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 0);
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assert_eq!(format!("{:x}", cb), "f6c0ff");
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}
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#[test]
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fn test_emit_test_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.test(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 0);
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assert_eq!(format!("{:x}", cb), "49bbffffffffffff00004c85d8");
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}
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#[test]
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fn test_emit_xor_lt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.xor(Opnd::Reg(RAX_REG), Opnd::UImm(0xFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c04881f0ff000000");
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}
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#[test]
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fn test_emit_xor_gt_32_bits() {
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let (mut asm, mut cb) = setup_asm();
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asm.xor(Opnd::Reg(RAX_REG), Opnd::UImm(0xFFFF_FFFF_FFFF));
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asm.compile_with_num_regs(&mut cb, 1);
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assert_eq!(format!("{:x}", cb), "4889c049bbffffffffffff00004c31d8");
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}
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}
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