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Add 1 more allocatable reg on arm

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Maxime Chevalier-Boisvert 2022-08-02 15:36:27 -04:00 committed by Takashi Kokubun
parent ca68ccdadd
commit 9db2ca723c
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2 changed files with 12 additions and 1 deletions
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11
.cirrus.yml
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@ -153,4 +153,15 @@ yjit_task:
bootstraptest/test_struct.rb \
bootstraptest/test_yjit_new_backend.rb \
bootstraptest/test_yjit_rust_port.rb
# These are the btests we can't run yet on arm:
#bootstraptest/test_block.rb (missing opt_send)
#bootstraptest/test_insns.rb (missing opt_send)
#bootstraptest/test_literal.rb (displacement bug)
#bootstraptest/test_syntax.rb (missing opt_send)
#bootstraptest/test_thread.rb (deadlock)
#bootstraptest/test_yjit.rb (multiple bugs)
#bootstraptest/test_yjit_30k_ifelse.rb (missing opt_send)
#bootstraptest/test_yjit_30k_methods.rb (missing opt_send)
# full_build_script: make -j

2
yjit/src/backend/arm64/mod.rs
View file

@ -66,7 +66,7 @@ impl Assembler
/// Note: we intentionally exclude C_RET_REG (X0) from this list
/// because of the way it's used in gen_leave() and gen_leave_exit()
pub fn get_alloc_regs() -> Vec<Reg> {
vec![X11_REG, X12_REG]
vec![X11_REG, X12_REG, X13_REG]
}
/// Get a list of all of the caller-saved registers