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* vm.h: add VM_FRAME_TYPE() and VM_FRAME_FLAG(). * cont.c, insnhelper.ci, insns.def, vm.c, vm_dump.c, vm_evalbody.ci, yarvcore.c: apply above changes. git-svn-id: svn+ssh://ci.ruby-lang.org/ruby/trunk@12706 b2dd03c8-39d4-4d8f-98ff-823fe69b080e
145 lines
2.7 KiB
C
145 lines
2.7 KiB
C
/* -*-c-*- */
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/**********************************************************************
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vm_evalbody.ci -
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$Author$
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$Date$
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Copyright (C) 2004-2006 Koichi Sasada
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**********************************************************************/
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#include <math.h>
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#if VMDEBUG > 0
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#define DECL_SC_REG(type, r, reg) register type reg_##r
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#elif __GNUC__ && __x86_64
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#define DECL_SC_REG(type, r, reg) register type reg_##r asm("r" reg)
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#elif __GNUC__ && __i386__
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#define DECL_SC_REG(type, r, reg) register type reg_##r asm("e" reg)
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#else
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#define DECL_SC_REG(type, r, reg) register type reg_##r
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#endif
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/* #define DECL_SC_REG(r, reg) VALUE reg_##r */
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typedef rb_iseq_t *ISEQ;
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#if !OPT_CALL_THREADED_CODE
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VALUE
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vm_eval(rb_thread_t *th, VALUE initial)
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{
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#if OPT_STACK_CACHING
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#if 0
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#elif __GNUC__ && __x86_64
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DECL_SC_REG(VALUE, a, "12");
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DECL_SC_REG(VALUE, b, "13");
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#else
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register VALUE reg_a;
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register VALUE reg_b;
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#endif
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#endif
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#if __GNUC__ && __i386__
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DECL_SC_REG(VALUE *, pc, "di");
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DECL_SC_REG(rb_control_frame_t *, cfp, "si");
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#define USE_MACHINE_REGS 1
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#elif __GNUC__ && __x86_64__
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DECL_SC_REG(VALUE *, pc, "14");
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DECL_SC_REG(rb_control_frame_t *, cfp, "15");
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#define USE_MACHINE_REGS 1
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#else
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register rb_control_frame_t *reg_cfp;
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VALUE *reg_pc;
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#endif
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#if USE_MACHINE_REGS
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#undef RESTORE_REGS
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#define RESTORE_REGS() \
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{ \
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REG_CFP = th->cfp; \
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reg_pc = reg_cfp->pc; \
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}
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#undef REG_PC
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#define REG_PC reg_pc
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#undef GET_PC
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#define GET_PC() (reg_pc)
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#undef SET_PC
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#define SET_PC(x) (reg_cfp->pc = REG_PC = (x))
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#endif
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#if OPT_TOKEN_THREADED_CODE || OPT_DIRECT_THREADED_CODE
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#include "vmtc.inc"
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if (th == 0) {
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#if OPT_STACK_CACHING
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yarv_finish_insn_seq[0] = (VALUE)&&LABEL (finish_SC_ax_ax);
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#else
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yarv_finish_insn_seq[0] = (VALUE)&&LABEL (finish);
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#endif
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return (VALUE)insns_address_table;
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}
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#endif
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reg_cfp = th->cfp;
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reg_pc = reg_cfp->pc;
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#if OPT_STACK_CACHING
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reg_a = initial;
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reg_b = 0;
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#endif
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first:
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INSN_DISPATCH();
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/*****************/
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#include "vm.inc"
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/*****************/
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END_INSNS_DISPATCH();
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/* unreachable */
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rb_bug("vm_eval: unreachable");
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return Qundef;
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}
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#else
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#include "vm.inc"
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#include "vmtc.inc"
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void **
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get_insns_address_table()
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{
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return (void **)insns_address_table;
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}
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VALUE
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vm_eval(rb_thread_t *th, VALUE initial)
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{
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register rb_control_frame_t *reg_cfp = th->cfp;
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VALUE ret;
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while (*GET_PC()) {
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reg_cfp = ((rb_insn_func_t) (*GET_PC()))(th, reg_cfp);
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if (reg_cfp == 0) {
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VALUE err = th->errinfo;
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th->errinfo = Qnil;
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return err;
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}
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}
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if (VM_FRAME_TYPE(th->cfp) != FRAME_MAGIC_FINISH) {
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rb_bug("cfp consistency error");
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}
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ret = *(th->cfp->sp-1); /* pop */
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th->cfp++; /* pop cf */
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return ret;
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}
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#endif
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