Failsafe, clear SPSel for sure

2023-02-13 20:54:32 -05:00 · 2019-02-23 14:34:03 +01:00 · 2019-02-23 14:34:03 +01:00 · 039bd191de
commit 039bd191de
parent bb977ac635
2 changed files with 2 additions and 0 deletions
--- a/aarch64-rpi/boot.S
+++ b/aarch64-rpi/boot.S
@ -95,6 +95,8 @@ _start:
    // set up exception handlers
 1:  ldr     x2, =_vectors
    msr     vbar_el1, x2
+    // disable execution level dependent stacks, so that we have only 4 vectors
+    msr     SPSel, #0
    // read cpu id, start slave cores
    mrs     x7, mpidr_el1
    and     x7, x7, #3
--- a/bootboot.img
+++ b/bootboot.img