mirror of
https://gitlab.com/bztsrc/bootboot.git
synced 2023-02-13 20:54:32 -05:00
More SMP stuff
This commit is contained in:
bzt
parent
e0dc1c152d
commit
b556210529
7 changed files with 311 additions and 284 deletions
BIN
dist/bootboot.bin
vendored
BIN
dist/bootboot.bin
vendored
Binary file not shown.
BIN
dist/bootboot.efi
vendored
BIN
dist/bootboot.efi
vendored
Binary file not shown.
BIN
dist/bootboot.rom
vendored
BIN
dist/bootboot.rom
vendored
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File diff suppressed because one or more lines are too long
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@ -102,6 +102,12 @@ macro prot_readsector
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call near prot_readsectorfunc
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}
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macro prot_sleep delay
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{
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mov ecx, delay
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call near prot_sleepfunc
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}
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macro DBG msg
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{
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if BBDEBUG eq 1
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@ -359,12 +365,15 @@ realmode_start:
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cmp ax, 0600h
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jb .cpuerror
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;look for minimum feature flags
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;so we have PAE?
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;do we have PAE?
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bt edx, 6
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jnc .cpuerror
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;what about MSR?
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bt edx, 5
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jnc .cpuerror
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;do we have RDTSC instruction?
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bt edx, 4
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jnc .cpuerror
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;and can we use long mode (LME)?
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mov eax, 80000000h
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mov ebp, eax
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@ -491,6 +500,21 @@ a20wait2: in al, 64h
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jz a20wait2
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ret
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a20ok:
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; calibrate RDTSC
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rdtsc
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mov dword [ncycles], eax
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mov dword [ncycles+4], edx
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; wait 200 usec
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xor cx, cx
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mov dx, 200
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mov ah, 086h
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int 15h
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rdtsc
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sub eax, dword [ncycles]
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sbb edx, dword [ncycles+4]
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mov dword [ncycles], eax
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mov dword [ncycles+4], edx
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; wait for a key press for half a sec, if pressed use backup initrd
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mov word [origcount], 0
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sti
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@ -834,7 +858,7 @@ ap_start: xor ax, ax
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mov eax, dword [esi]
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or ah, 1h
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mov dword [esi], eax
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inc byte [ap_done]
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lock inc byte [ap_done]
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; spinlock until BSP finishes
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@@: pause
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cmp byte [bsp_done], 0
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@ -1074,6 +1098,26 @@ prot_oct2bin:
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pop ebx
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ret
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; IN: ecx delay time in 200 usec units
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prot_sleepfunc:
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push edx
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rdtsc
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mov dword [gpt_ptr], eax
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mov dword [gpt_ptr+4], edx
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mov eax, dword [ncycles]
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mov edx, dword [ncycles+4]
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mul ecx
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add dword [gpt_ptr], eax
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adc dword [gpt_ptr+4], edx
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@@: pause
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rdtsc
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cmp dword [gpt_ptr+4], edx
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jl @b
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cmp dword [gpt_ptr], eax
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jl @b
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pop edx
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ret
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; IN: al, character to send
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uart_send: mov ah, al
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mov dx, word [400h] ;3fdh
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@ -1971,38 +2015,35 @@ end if
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mov edi, lapic_ids
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.nextmadtentry:
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cmp word [numcores], 256
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jae .dosmp
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jae .acpidone
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cmp byte [ebx], 0 ; madt_entry.type: is it a Local APIC Processor?
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jne @f
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mov al, byte [ebx+4] ; madt_entry.lapicproc.flag & ENABLED
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and al, 1
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jz .madterr
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jz @f
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xor ax, ax
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mov al, byte [ebx+3] ; madt_entry.lapicproc.lapicid
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cmp al, 0FFh
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je .madterr
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je @f
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stosw ; ACPI table holds 1 byte id, but internally we have 2 bytes
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inc word [numcores]
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jmp @f
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.madterr: mov byte [boguscore], 1
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@@: xor eax, eax
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mov al, byte [ebx+1] ; madt_entry.size
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or al, al
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jz .dosmp
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jz .acpidone
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add ebx, eax
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cmp ecx, eax
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jl .acpidone
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sub ecx, eax
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cmp ecx, 0
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jg .nextmadtentry
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jmp .dosmp
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jmp .nextmadtentry
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.trymp: ; in lack of ACPI, try legacy MP structures
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mov esi, dword [bootboot.mp_ptr]
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or esi, esi
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jz .nosmp
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jz .acpidone
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mov esi, dword [esi+4]
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cmp dword [esi], 'PCMP'
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jne .nosmp
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jne .acpidone
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mov eax, dword [esi+36] ; pcmp.lapic_address
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mov dword [lapic_ptr], eax
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mov cx, word [esi+34] ; pcmp.numentries
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@ -2010,7 +2051,7 @@ end if
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mov edi, lapic_ids
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.nextpcmpentry:
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cmp word [numcores], 256
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jae .dosmp
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jae .acpidone
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cmp byte [esi], 0 ; pcmp_entry.type: is it a Local APIC Processor?
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jne @f
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xor ax, ax
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@ -2021,13 +2062,18 @@ end if
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@@: add esi, 8
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dec cx
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jnz .nextpcmpentry
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; send IPI and SIPI
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.dosmp: cmp word [numcores], 2
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jb .nosmp
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.acpidone:
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; failsafe
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cmp dword [lapic_ptr], 0
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jz .nosmp
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jz @f
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cmp word [numcores], 0
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jnz .smpok
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@@: mov word [numcores], 1
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mov ax, word [bootboot.bspid]
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mov word [lapic_ids], ax
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mov dword [lapic_ptr], 0
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jmp .stks
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.smpok:
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if BBDEBUG eq 1
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xor eax, eax
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mov dword [gpt_ptr], eax
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@ -2069,196 +2115,11 @@ if BBDEBUG eq 1
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call real_printfunc
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mov si, gpt_ptr
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call real_printfunc
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cmp byte [boguscore], 0
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jz @f
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mov si, dbg_bogus
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call real_printfunc
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@@: mov si, crlf
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mov si, crlf
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call real_printfunc
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real_protmode
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end if
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; relocate AP trampoline
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mov esi, ap_trampoline
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mov edi, 7000h
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mov ecx, (ap_start-ap_trampoline+3)/4
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repnz movsd
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; enable Local APIC
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mov esi, dword [lapic_ptr]
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add esi, 0F0h
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mov eax, dword [esi]
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or ah, 1h
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mov dword [esi], eax
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cmp byte [boguscore], 0
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jnz .nobcast
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; send Broadcast INIT IPI
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mov esi, dword [lapic_ptr]
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add esi, 300h
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mov eax, 0C4500h
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mov dword [esi], eax
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; wait 10 millisec
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push esi
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prot_realmode
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xor cx, cx
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mov dx, 10000
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop esi
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; send Broadcast STARTUP IPI
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mov eax, 0C4607h ; start at 0700:0000h
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mov dword [esi], eax
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; wait 200 microsec
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push eax
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push esi
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prot_realmode
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xor cx, cx
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mov dx, 200
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop esi
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pop eax
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mov dword [esi], eax ; second SIPI
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jmp .nosmp
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; send IPIs to specific cores one by one
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.nobcast: xor edx, edx
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.nextcore: cmp dx, word [numcores]
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jae .nosmp
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xor esi, esi
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mov esi, edx
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inc edx
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shl esi, 1
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add esi, lapic_ids
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mov bx, word [esi]
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cmp bx, word [bootboot.bspid]
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je .nextcore
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shl ebx, 24
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; clear APIC error
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mov esi, dword [lapic_ptr]
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add esi, 280h
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mov dword [esi], 0
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mov eax, dword [esi]
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; select AP
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add esi, 30h
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mov dword [esi], ebx
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; trigger INIT IPI
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sub esi, 10h
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mov eax, 004500h
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mov dword [esi], eax
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; wait 200 microsec
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push esi
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push edx
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push ebx
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prot_realmode
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xor cx, cx
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mov dx, 200
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop ebx
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pop edx
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pop esi
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; select AP
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add esi, 10h
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mov dword [esi], ebx
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; deassert INIT IPI
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sub esi, 10h
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mov eax, 008500h
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mov dword [esi], eax
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; wait 10 millisec
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push esi
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push edx
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push ebx
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prot_realmode
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xor cx, cx
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mov dx, 10000
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop ebx
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pop edx
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pop esi
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mov byte [ap_done], 0
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; select AP
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add esi, 10h
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mov dword [esi], ebx
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; send STARTUP IPI
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sub esi, 10h
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mov eax, 004607h ; start at 0700:0000h
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mov dword [esi], eax
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; wait 200 microsec
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push eax
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push esi
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push edx
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push ebx
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prot_realmode
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xor cx, cx
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mov dx, 200
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop ebx
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pop edx
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pop esi
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pop eax
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; do we need a second SIPI?
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cmp byte [ap_done], 0
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jnz .nextcore
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; select AP
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add esi, 10h
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mov dword [esi], ebx
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; send STARTUP IPI
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sub esi, 10h
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mov dword [esi], eax
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; wait 200 microsec
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push edx
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prot_realmode
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xor cx, cx
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mov dx, 200
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mov ah, 086h
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sti
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int 15h
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cli
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real_protmode
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pop edx
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jmp .nextcore
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.nosmp: ; failsafe
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cmp word [numcores], 0
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jnz @f
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inc word [numcores]
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mov ax, word [bootboot.bspid]
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mov word [lapic_ids], ax
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mov dword [lapic_ptr], 0
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@@: ; remove core stacks from memory map
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.stks: ; remove core stacks from memory map
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xor eax, eax
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mov ax, word [numcores]
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shl eax, 10
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@ -2498,16 +2359,176 @@ end if
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stosd
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stosd
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;Enter long mode
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cli
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mov al, 0FFh ;disable PIC
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out 021h, al
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out 0A1h, al
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in al, 70h ;disable NMI
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or al, 80h
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out 70h, al
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; send IPI and SIPI
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cmp word [numcores], 2
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jb .nosmp
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cmp dword [lapic_ptr], 0
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jz .nosmp
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; relocate AP trampoline
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mov esi, ap_trampoline
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mov edi, 7000h
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mov ecx, (ap_start-ap_trampoline+3)/4
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repnz movsd
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; enable Local APIC
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mov esi, dword [lapic_ptr]
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add esi, 0D0h ; logical destination
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mov al, 1
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shl eax, 24
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mov dword [esi], eax
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add esi, 10h ; destination form
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xor eax, eax
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sub eax, 1
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mov dword [esi], eax
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add esi, 10h
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mov eax, dword [esi] ; spurious + enable
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mov ax, 1FFh
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mov dword [esi], eax
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sub esi, 70h ; task priority
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xor eax, eax
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mov dword [esi], eax
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; make sure we use the correct Local APIC ID for the BSP
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sub esi, 60h
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mov eax, dword [esi]
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shr eax, 24
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mov word [bootboot.bspid], ax
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; send IPIs to specific cores one by one
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xor edx, edx
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.initcore: cmp dx, word [numcores]
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jae .sipi
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mov esi, edx
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inc edx
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shl esi, 1
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add esi, lapic_ids
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mov bx, word [esi]
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cmp bx, word [bootboot.bspid]
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je .initcore
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shl ebx, 24
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; clear APIC error
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mov esi, dword [lapic_ptr]
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add esi, 280h
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mov dword [esi], 0
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mov eax, dword [esi]
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add esi, 20h
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; select AP
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@@: pause
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mov eax, dword [esi]
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bt eax, 12
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jc @b
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add esi, 10h
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mov eax, dword [esi]
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and eax, 00ffffffh
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or eax, ebx
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mov dword [esi], eax
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; trigger INIT IPI
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sub esi, 10h
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mov eax, dword [esi]
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and eax, 0fff00000h
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or eax, 00C500h
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mov dword [esi], eax
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; wait 200 microsec
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prot_sleep 1
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; select AP
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@@: pause
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mov eax, dword [esi]
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bt eax, 12
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jc @b
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add esi, 10h
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mov eax, dword [esi]
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and eax, 00ffffffh
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or eax, ebx
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mov dword [esi], eax
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; deassert INIT IPI
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sub esi, 10h
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mov eax, dword [esi]
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and eax, 0fff00000h
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or eax, 008500h
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mov dword [esi], eax
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jmp .initcore
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.sipi:
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; wait 10 millisec
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prot_sleep 50
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xor edx, edx
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.nextcore: cmp dx, word [numcores]
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jae .nosmp
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mov esi, edx
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inc edx
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shl esi, 1
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add esi, lapic_ids
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mov bx, word [esi]
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cmp bx, word [bootboot.bspid]
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je .nextcore
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shl ebx, 24
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mov byte [ap_done], 0
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; select AP
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mov esi, dword [lapic_ptr]
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add esi, 300h
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@@: pause
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mov eax, dword [esi]
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bt eax, 12
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jc @b
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add esi, 10h
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mov eax, dword [esi]
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and eax, 00ffffffh
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or eax, ebx
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mov dword [esi], eax
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||||
; send STARTUP IPI
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||||
sub esi, 10h
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mov eax, dword [esi]
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and eax, 0fff0f800h
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or eax, 004607h ; start at 0700:0000h
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mov dword [esi], eax
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||||
|
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; wait 200 microsec
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prot_sleep 1
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; do we need a second SIPI?
|
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cmp byte [ap_done], 0
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jnz .nextcore
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; select AP
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||||
@@: pause
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mov eax, dword [esi]
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bt eax, 12
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||||
jc @b
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add esi, 10h
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||||
mov eax, dword [esi]
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||||
and eax, 00ffffffh
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||||
or eax, ebx
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||||
mov dword [esi], eax
|
||||
; send STARTUP IPI
|
||||
sub esi, 10h
|
||||
mov eax, dword [esi]
|
||||
and eax, 0fff0f800h
|
||||
or eax, 004607h
|
||||
mov dword [esi], eax
|
||||
|
||||
; wait 200 microsec
|
||||
prot_sleep 1
|
||||
jmp .nextcore
|
||||
.nosmp:
|
||||
|
||||
;Enter long mode
|
||||
cli
|
||||
;release AP spinlock
|
||||
inc byte [bsp_done]
|
||||
lock inc byte [bsp_done]
|
||||
|
||||
;don't use stack below this line
|
||||
longmode_init:
|
||||
|
|
@ -2533,7 +2554,7 @@ longmode_init:
|
|||
mov ss, ax
|
||||
mov fs, ax
|
||||
mov gs, ax
|
||||
lock inc word [bootboot.numcores]
|
||||
lock inc word [bootboot.numcores]
|
||||
; find out our lapic id
|
||||
mov eax, dword [lapic_ptr]
|
||||
or eax, eax
|
||||
|
|
@ -2918,9 +2939,8 @@ hasconfig: db 0
|
|||
iscdrom: db 0
|
||||
nosmp: db 0
|
||||
numcores: dw 0
|
||||
ap_done:
|
||||
boguscore: db 0
|
||||
bsp_done: ;flag to indicate APs can run
|
||||
ap_done: db 0
|
||||
bsp_done: db 0 ;flag to indicate APs can run
|
||||
fattype: db 0
|
||||
bkp: dd ' '
|
||||
if BBDEBUG eq 1
|
||||
|
|
@ -2939,7 +2959,6 @@ dbg_scan db " * Autodetecting kernel",10,13,0
|
|||
dbg_elf db " * Parsing ELF64",10,13,0
|
||||
dbg_pe db " * Parsing PE32+",10,13,0
|
||||
dbg_smp db " * SMP numcores ",0
|
||||
dbg_bogus db " (bogus ACPI table)",0
|
||||
dbg_vesa db " * Screen VESA VBE",10,13,0
|
||||
end if
|
||||
backup: db " * Backup initrd",10,13,0
|
||||
|
|
@ -2989,6 +3008,7 @@ core_len: dd ?
|
|||
gpt_ptr: dd ?
|
||||
gpt_num: dd ?
|
||||
gpt_ent: dd ?
|
||||
ncycles: dq ?
|
||||
lapic_ptr: dd ?
|
||||
lapic_ids:
|
||||
tinf_bss_start:
|
||||
|
|
|
|||
|
|
@ -76,10 +76,11 @@ extern void bsp64_init(uint64_t apicid);
|
|||
extern void bsp_init();
|
||||
#endif
|
||||
|
||||
#define send_ipi(a,v) do { \
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x310)) = (a << 24); \
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) = v; \
|
||||
#define send_ipi(a,m,v) do { \
|
||||
while(*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) & (1 << 12)) __asm__ __volatile__ ("pause" : : : "memory"); \
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x310)) = (*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x310)) & \
|
||||
0x00ffffff) | (a << 24); \
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) = (*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) & m) | v; \
|
||||
} while(0)
|
||||
|
||||
/*** ELF64 defines and structs ***/
|
||||
|
|
@ -760,7 +761,7 @@ void MapPage(uint64_t virt, uint64_t phys)
|
|||
*/
|
||||
int main(void)
|
||||
{
|
||||
int ret=0, i, dsk, boguscore = 0, numcores = 0;
|
||||
int ret=0, i, dsk, numcores = 0;
|
||||
uint8_t *pe, *ptr;
|
||||
uint32_t np,sp,r;
|
||||
unsigned char *data;
|
||||
|
|
@ -1132,8 +1133,6 @@ gzerr: panic("Unable to uncompress");
|
|||
case 0: // found Processor Local APIC
|
||||
if((ptr[4] & 1) && ptr[3] != 0xFF && lapic_ids[(int)ptr[3]] == 0xFFFF)
|
||||
lapic_ids[(int)ptr[3]] = i++;
|
||||
else
|
||||
boguscore++;
|
||||
break;
|
||||
case 5: lapic_addr = *((uint64_t*)(ptr+4)); break; // found 64 bit Local APIC Address
|
||||
}
|
||||
|
|
@ -1143,38 +1142,43 @@ gzerr: panic("Unable to uncompress");
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
// disable PIC and NMI
|
||||
__asm__ __volatile__ (
|
||||
"movb $0xFF, %%al; outb %%al, $0x21; outb %%al, $0xA1;" // disable PIC
|
||||
"inb $0x70, %%al; orb $0x80, %%al; outb %%al, $0x70;" // disable NMI
|
||||
: : :);
|
||||
|
||||
if(!nosmp && numcores > 1 && lapic_addr) {
|
||||
DBG(" * SMP numcores %d%s\n", numcores, boguscore ? " (bogus ACPI table)" : "");
|
||||
DBG(" * SMP numcores %d\n", numcores);
|
||||
memcpy((uint8_t*)0x1000, &ap_trampoline, 128);
|
||||
|
||||
// enable Local APIC
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x0D0)) = (1 << 24);
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x0E0)) = 0xFFFFFFFF;
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x0F0)) = *((volatile uint32_t*)((uintptr_t)lapic_addr + 0x0F0)) | 0x100;
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x080)) = 0;
|
||||
// make sure we use the correct Local APIC ID for the BSP
|
||||
bootboot->bspid = *((volatile uint32_t*)((uintptr_t)lapic_addr + 0x20)) >> 24;
|
||||
|
||||
// if there were no bogus core definitions in the ACPI table, we can do a broadcast (simpler, faster)
|
||||
if(!boguscore) {
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) = 0x0C4500; // trigger bcast INIT IPI
|
||||
mdelay(10); // wait 10 msec
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) = 0x0C4601; // trigger bcast SIPI, start at 0100:0000h
|
||||
udelay(200); // wait 200 usec
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x300)) = 0x0C4601; // trigger second bcast SIPI
|
||||
} else {
|
||||
// supports up to 255 cores (lapicid 255 is bcast address), requires x2APIC to have more
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x280)) = 0; // clear APIC errors
|
||||
r = *((volatile uint32_t*)((uintptr_t)lapic_addr + 0x280));
|
||||
send_ipi(i, 0x004500); // trigger INIT IPI
|
||||
}
|
||||
mdelay(10); // wait 10 msec
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((uint8_t*)0x1011) = 0;
|
||||
send_ipi(i, 0x004601); // trigger SIPI, start at 0100:0000h
|
||||
udelay(200); // wait 200 usec
|
||||
if(!*((uint8_t*)0x1011)) {
|
||||
send_ipi(i, 0x004601);
|
||||
udelay(200);
|
||||
}
|
||||
// supports up to 255 cores (lapicid 255 is bcast address), requires x2APIC to have more
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((volatile uint32_t*)((uintptr_t)lapic_addr + 0x280)) = 0; // clear APIC errors
|
||||
r = *((volatile uint32_t*)((uintptr_t)lapic_addr + 0x280));
|
||||
send_ipi(i, 0xfff00000, 0x00C500); // trigger INIT IPI
|
||||
udelay(200);
|
||||
send_ipi(i, 0xfff00000, 0x008500); // deassert INIT IPI
|
||||
}
|
||||
mdelay(10); // wait 10 msec
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((uint8_t*)0x1011) = 0;
|
||||
send_ipi(i, 0xfff0f800, 0x004601); // trigger SIPI, start at 0100:0000h
|
||||
udelay(200); // wait 200 usec
|
||||
if(!*((uint8_t*)0x1011)) {
|
||||
send_ipi(i, 0xfff0f800, 0x004601);
|
||||
udelay(200);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -1542,10 +1542,10 @@ efi_main (EFI_HANDLE image, EFI_SYSTEM_TABLE *systab)
|
|||
} else \
|
||||
__asm__ __volatile__ ("1: pause; dec %%ecx; or %%ecx, %%ecx; jnz 1b" : : "c"(n*1000) : "memory"); \
|
||||
} while(0)
|
||||
#define send_ipi(a,v) do { \
|
||||
*((volatile uint32_t*)(lapic_addr + 0x310)) = (a << 24); \
|
||||
*((volatile uint32_t*)(lapic_addr + 0x300)) = v; \
|
||||
#define send_ipi(a,m,v) do { \
|
||||
while(*((volatile uint32_t*)(lapic_addr + 0x300)) & (1 << 12)) __asm__ __volatile__ ("pause" : : : "memory"); \
|
||||
*((volatile uint32_t*)(lapic_addr + 0x310)) = (*((volatile uint32_t*)(lapic_addr + 0x310)) & 0x00ffffff) | (a << 24); \
|
||||
*((volatile uint32_t*)(lapic_addr + 0x300)) = (*((volatile uint32_t*)(lapic_addr + 0x300)) & m) | v; \
|
||||
} while(0)
|
||||
#endif
|
||||
|
||||
|
|
@ -1922,7 +1922,7 @@ gzerr: return report(EFI_COMPROMISED_DATA,L"Unable to uncompress");
|
|||
numcores = 1;
|
||||
#else
|
||||
UINT8 *ptr = (UINT8*)bootboot->arch.x86_64.acpi_ptr, *pe, *data;
|
||||
UINT64 r, boguscore = 0;
|
||||
UINT64 r;
|
||||
for(i = 0; i < (int)(sizeof(lapic_ids)/sizeof(lapic_ids[0])); i++) lapic_ids[i] = 0xFFFF;
|
||||
if(!nosmp && ptr && (ptr[0]=='X' || ptr[0]=='R') && ptr[1]=='S' && ptr[2]=='D' && ptr[3]=='T') {
|
||||
pe = ptr; ptr += 36;
|
||||
|
|
@ -1938,8 +1938,6 @@ gzerr: return report(EFI_COMPROMISED_DATA,L"Unable to uncompress");
|
|||
case 0: // found Processor Local APIC
|
||||
if((ptr[4] & 1) && ptr[3] != 0xFF && lapic_ids[(INTN)ptr[3]] == 0xFFFF)
|
||||
lapic_ids[(INTN)ptr[3]] = i++;
|
||||
else
|
||||
boguscore++;
|
||||
break;
|
||||
case 5: lapic_addr = *((uint64_t*)(ptr+4)); break; // found 64 bit Local APIC Address
|
||||
}
|
||||
|
|
@ -1949,7 +1947,7 @@ gzerr: return report(EFI_COMPROMISED_DATA,L"Unable to uncompress");
|
|||
if(bsp_num == 0xFFFF) bsp_num = 0;
|
||||
else {
|
||||
numcores = i;
|
||||
DBG(L" * SMP numcores %d%s\n", numcores, boguscore ? L" (bogus ACPI table)" : L"");
|
||||
DBG(L" * SMP numcores %d\n", numcores);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
|
@ -2094,6 +2092,12 @@ get_memory_map:
|
|||
return report(status,L"ExitBootServices");
|
||||
}
|
||||
|
||||
// disable PIC and NMI
|
||||
__asm__ __volatile__ (
|
||||
"movb $0xFF, %%al; outb %%al, $0x21; outb %%al, $0xA1;" // disable PIC
|
||||
"inb $0x70, %%al; orb $0x80, %%al; outb %%al, $0x70;" // disable NMI
|
||||
: : :);
|
||||
|
||||
#if !defined(USE_MP_SERVICES) || !USE_MP_SERVICES
|
||||
// green dot on the top left corner (do not allow gcc to rearrange this!!!)
|
||||
*((volatile uint64_t*)(bootboot->fb_ptr)) =
|
||||
|
|
@ -2110,36 +2114,34 @@ get_memory_map:
|
|||
"movl %%cs, %%eax; movl %%eax, 0x80CC;"
|
||||
"movl %%ds, %%eax; movl %%eax, 0x80D0;"
|
||||
"movq %%rbx, 0x80D8;"
|
||||
"sgdt 0x80E0;" : : "a"((uint64_t)&ap_trampoline), "b"((uint64_t)&bootboot_startcore) : );
|
||||
"sgdt 0x80E0;" : : "d"((uint64_t)&ap_trampoline), "b"((uint64_t)&bootboot_startcore) : );
|
||||
|
||||
// enable Local APIC
|
||||
*((volatile uint32_t*)(lapic_addr + 0x0F0)) = *((volatile uint32_t*)(lapic_addr + 0x0F0)) | 0x100;
|
||||
*((volatile uint32_t*)(lapic_addr + 0x0D0)) = (1 << 24);
|
||||
*((volatile uint32_t*)(lapic_addr + 0x0E0)) = 0xFFFFFFFF;
|
||||
*((volatile uint32_t*)(lapic_addr + 0x0F0)) = *((volatile uint32_t*)(lapic_addr + 0x0F0)) | 0x1FF;
|
||||
*((volatile uint32_t*)(lapic_addr + 0x080)) = 0;
|
||||
// make sure we use the correct Local APIC ID for the BSP
|
||||
bootboot->bspid = *((volatile uint32_t*)(lapic_addr + 0x20)) >> 24;
|
||||
|
||||
// if there were no bogus core definitions in the ACPI table, we can do a broadcast (simpler, faster)
|
||||
if(!boguscore) {
|
||||
*((volatile uint32_t*)(lapic_addr + 0x300)) = 0x0C4500; // trigger bcast INIT IPI
|
||||
sleep(50); // wait 10 msec
|
||||
*((volatile uint32_t*)(lapic_addr + 0x300)) = 0x0C4608; // trigger bcast SIPI, start at 0800:0000h
|
||||
sleep(1); // wait 200 usec
|
||||
*((volatile uint32_t*)(lapic_addr + 0x300)) = 0x0C4608; // trigger second bcast SIPI
|
||||
} else {
|
||||
// supports up to 255 cores (lapicid 255 is bcast address), requires x2APIC to have more
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((volatile uint32_t*)(lapic_addr + 0x280)) = 0; // clear APIC errors
|
||||
a = *((volatile uint32_t*)((uintptr_t)lapic_addr + 0x280));
|
||||
send_ipi(i, 0x004500); // trigger INIT IPI
|
||||
}
|
||||
sleep(50); // wait 10 msec
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
ap_done = 0;
|
||||
send_ipi(i, 0x004608); // trigger SIPI, start at 0800:0000h
|
||||
sleep(1); // wait 200 usec
|
||||
if(!ap_done) {
|
||||
send_ipi(i, 0x004608);
|
||||
sleep(1);
|
||||
}
|
||||
// supports up to 255 cores (lapicid 255 is bcast address), requires x2APIC to have more
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
*((volatile uint32_t*)(lapic_addr + 0x280)) = 0; // clear APIC errors
|
||||
a = *((volatile uint32_t*)(lapic_addr + 0x280));
|
||||
send_ipi(i, 0xfff00000, 0x00C500); // trigger INIT IPI
|
||||
sleep(1);
|
||||
send_ipi(i, 0xfff00000, 0x008500); // deassert INIT IPI
|
||||
}
|
||||
sleep(50); // wait 10 msec
|
||||
for(i = 0; i < 255; i++) {
|
||||
if(i == bootboot->bspid || lapic_ids[i] == 0xFFFF) continue;
|
||||
ap_done = 0;
|
||||
send_ipi(i, 0xfff0f800, 0x004608); // trigger SIPI, start at 0800:0000h
|
||||
sleep(1); // wait 200 usec
|
||||
if(!ap_done) {
|
||||
send_ipi(i, 0xfff0f800, 0x004608);
|
||||
sleep(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -2156,6 +2158,7 @@ get_memory_map:
|
|||
|
||||
// release AP spinlock
|
||||
bsp_done = 1;
|
||||
__asm__ __volatile__ ("pause" : : : "memory"); // memory barrier
|
||||
bootboot_startcore((VOID*)bsp_num);
|
||||
}
|
||||
return report(status,L"Initrd not found");
|
||||
|
|
|
|||
Loading…
Reference in a new issue