mirror of
https://gitlab.com/bztsrc/bootboot.git
synced 2023-02-13 20:54:32 -05:00
Support for RPi4
This commit is contained in:
bzt
parent
2df6cb68bd
commit
cadd7dd625
15 changed files with 97 additions and 94 deletions
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@ -11,7 +11,7 @@ Előre lefordított binárisok mellékelve, egyből használhatók.
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Ha újra akarod fordítani, szükséged lesz a fasm-ra (nincs mellékelve).
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[boot.bin](https://gitlab.com/bztsrc/bootboot/raw/master/boot.bin) (512 bájt, egyszerre MBR, VBR és CDROM indító szektor), [bootboot.bin](https://gitlab.com/bztsrc/bootboot/raw/master/bootboot.bin) (11k, a boot.bin tölti be, valamint BBS bővítő ROM és Multiboot kompatíbilis is)
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3. *aarch64-rpi* ARMv8 betöltő Raspberry Pi 3-hoz
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3. *aarch64-rpi* ARMv8 betöltő Raspberry Pi 3-hoz, 4-hez
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[bootboot.img](https://gitlab.com/bztsrc/bootboot/raw/master/bootboot.img) (32k)
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4. *mykernel* egy példa BOOTBOOT [kompatíbilis kernel](https://gitlab.com/bztsrc/bootboot/tree/master/mykernel) C-ben írva, ami vonalakat húz meg színes dobozokat rajzol
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@ -36,7 +36,7 @@ Multiboottal, láncbetöltéssel MBR, VBR (GPT hibrid indítás) és CDROM indí
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Az [UEFI gépek](https://gitlab.com/bztsrc/bootboot/tree/master/x86_64-efi)en egy szabványos OS Loader alkalmazás.
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A [Raspberry Pi 3](https://gitlab.com/bztsrc/bootboot/tree/master/aarch64-rpi) gépen a bootboot.img-t a start.elf
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A [Raspberry Pi 3+](https://gitlab.com/bztsrc/bootboot/tree/master/aarch64-rpi) gépen a bootboot.img-t a start.elf
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tölti be kernel8.img néven az SD kártya első partíciójáról.
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A különbség más betöltő protokollokhoz képest a rugalmasság és a hordozhatóság; a tisztán 64 bit támogatás; és hogy
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@ -332,7 +332,7 @@ elmehetsz egészen 16M-ig).
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3.2. *BIOS lemez*: másold a __bootboot.bin__-t az **_FS0:\BOOTBOOT\LOADER_**-be.
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3.3. *Raspberry Pi 3*: másold a __bootboot.img__-t az **_FS0:\KERNEL8.IMG_**-be.
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3.3. *Raspberry Pi 3+*: másold a __bootboot.img__-t az **_FS0:\KERNEL8.IMG_**-be.
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**FONTOS**: olvasd el a kérdéses implementáció README.md-jét is.
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@ -11,7 +11,7 @@ I provide pre-compiled images ready for use.
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If you want to recompile this, you'll need fasm (not included).
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[boot.bin](https://gitlab.com/bztsrc/bootboot/raw/master/boot.bin) (512 bytes, works as MBR, VBR and CDROM boot record too), [bootboot.bin](https://gitlab.com/bztsrc/bootboot/raw/master/bootboot.bin) (11k, loaded by boot.bin, also BBS Expansion ROM and Multiboot compliant)
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3. *aarch64-rpi* ARMv8 boot loader for Raspberry Pi 3
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3. *aarch64-rpi* ARMv8 boot loader for Raspberry Pi 3, 4
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[bootboot.img](https://gitlab.com/bztsrc/bootboot/raw/master/bootboot.img) (32k)
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4. *mykernel* an example BOOTBOOT [compatible kernel](https://gitlab.com/bztsrc/bootboot/tree/master/mykernel) in C which draws lines and boxes
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@ -36,7 +36,7 @@ Multiboot, chainload from MBR, VBR (GPT hybrid booting) and CDROM boot record, o
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On [UEFI machines](https://gitlab.com/bztsrc/bootboot/tree/master/x86_64-efi), it is a standard EFI OS Loader application.
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On [Raspberry Pi 3](https://gitlab.com/bztsrc/bootboot/tree/master/aarch64-rpi) board the bootboot.img
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On [Raspberry Pi 3+](https://gitlab.com/bztsrc/bootboot/tree/master/aarch64-rpi) board the bootboot.img
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is loaded from the boot partition on SD card as kernel8.img by start.elf.
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The difference to other booting protocols is flexibility and portability;
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@ -334,7 +334,7 @@ You can also create an Option ROM out of INITRD (on BIOS there's not much space
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3.2. *BIOS disk*: copy __bootboot.bin__ to **_FS0:\BOOTBOOT\LOADER_**.
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3.3. *Raspberry Pi 3*: copy __bootboot.img__ to **_FS0:\KERNEL8.IMG_**.
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3.3. *Raspberry Pi 3+*: copy __bootboot.img__ to **_FS0:\KERNEL8.IMG_**.
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**IMPORTANT**: see the relevant port's README.md for more details.
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@ -1,9 +1,9 @@
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BOOTBOOT Raspberry Pi 3 Implementáció
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=====================================
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BOOTBOOT Raspberry Pi 3 / 4 Implementáció
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=========================================
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Általános leírásért lásd a [BOOTBOOT Protokoll](https://gitlab.com/bztsrc/bootboot)t.
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A [Raspberry Pi 3](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/sdcard.md) gépen a bootboot.img-t a
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A [Raspberry Pi 3+](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/sdcard.md) gépen a bootboot.img-t a
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start.elf tölti be kernel8.ig néven az SD kártya első partíciójáról. Ha külön förmver és boot partíciót szeretnél, olvasd el
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a [dokumentációt](https://gitlab.com/bztsrc/bootboot/blob/master/bootboot_spec_1st_ed.pdf).
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@ -1,9 +1,9 @@
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BOOTBOOT Raspberry Pi 3 Implementation
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======================================
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BOOTBOOT Raspberry Pi 3 / 4 Implementation
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==========================================
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See [BOOTBOOT Protocol](https://gitlab.com/bztsrc/bootboot) for common details.
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On [Raspberry Pi 3](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/sdcard.md) board the bootboot.img
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On [Raspberry Pi 3+](https://www.raspberrypi.org/documentation/hardware/raspberrypi/bootmodes/sdcard.md) board the bootboot.img
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is loaded from the boot (or firmware) partition on SD card as kernel8.img by start.elf. For separating firmware and boot
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partitions see [documentation](https://gitlab.com/bztsrc/bootboot/blob/master/bootboot_spec_1st_ed.pdf).
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@ -24,7 +24,7 @@
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* DEALINGS IN THE SOFTWARE.
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*
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* This file is part of the BOOTBOOT Protocol package.
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* @brief Boot loader for the Raspberry Pi 3+ ARMv8
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* @brief Boot loader for the Raspberry Pi 3 and 4 ARMv8
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*
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*/
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.section ".text.boot"
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@ -101,15 +101,11 @@ _start:
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mrs x7, mpidr_el1
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and x7, x7, #3
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cbnz x7, 3f
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// failsafe: if startup.elf does not start all cores (depends on config.txt), and qemu expects 0xD8
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mov x2, #0x40000000
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mov x3, #0xd8
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str w1, [x2, #0x9C] // write _start address to core1's mailbox 3
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str w1, [x3, #8]
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str w1, [x2, #0xAC] // write _start address to core2's mailbox 3
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str w1, [x3, #16]
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str w1, [x2, #0xBC] // write _start address to core3's mailbox 3
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str w1, [x3, #24]
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// start all cores
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mov x2, #0xd8
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str w1, [x2, #8]
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str w1, [x2, #16]
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str w1, [x2, #24]
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sev
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// clear bss
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ldr x2, =__bss_start
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@ -24,7 +24,7 @@
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* DEALINGS IN THE SOFTWARE.
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*
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* This file is part of the BOOTBOOT Protocol package.
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* @brief Boot loader for the Raspberry Pi 3+ ARMv8
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* @brief Boot loader for the Raspberry Pi 3 and 4 ARMv8
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*
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*/
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@ -136,55 +136,55 @@ typedef struct {
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/*** Raspberry Pi specific defines ***/
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#define MMIO_BASE 0x3F000000
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static uint64_t mmio_base;
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#define PM_RTSC ((volatile uint32_t*)(MMIO_BASE+0x0010001c))
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#define PM_WATCHDOG ((volatile uint32_t*)(MMIO_BASE+0x00100024))
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#define PM_RTSC ((volatile uint32_t*)(mmio_base+0x0010001c))
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#define PM_WATCHDOG ((volatile uint32_t*)(mmio_base+0x00100024))
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#define PM_WDOG_MAGIC 0x5a000000
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#define PM_RTSC_FULLRST 0x00000020
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#define GPFSEL0 ((volatile uint32_t*)(MMIO_BASE+0x00200000))
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#define GPFSEL1 ((volatile uint32_t*)(MMIO_BASE+0x00200004))
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#define GPFSEL2 ((volatile uint32_t*)(MMIO_BASE+0x00200008))
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#define GPFSEL3 ((volatile uint32_t*)(MMIO_BASE+0x0020000C))
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#define GPFSEL4 ((volatile uint32_t*)(MMIO_BASE+0x00200010))
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#define GPFSEL5 ((volatile uint32_t*)(MMIO_BASE+0x00200014))
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#define GPSET0 ((volatile uint32_t*)(MMIO_BASE+0x0020001C))
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#define GPSET1 ((volatile uint32_t*)(MMIO_BASE+0x00200020))
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#define GPCLR0 ((volatile uint32_t*)(MMIO_BASE+0x00200028))
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#define GPLEV0 ((volatile uint32_t*)(MMIO_BASE+0x00200034))
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#define GPLEV1 ((volatile uint32_t*)(MMIO_BASE+0x00200038))
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#define GPEDS0 ((volatile uint32_t*)(MMIO_BASE+0x00200040))
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#define GPEDS1 ((volatile uint32_t*)(MMIO_BASE+0x00200044))
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#define GPHEN0 ((volatile uint32_t*)(MMIO_BASE+0x00200064))
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#define GPHEN1 ((volatile uint32_t*)(MMIO_BASE+0x00200068))
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#define GPPUD ((volatile uint32_t*)(MMIO_BASE+0x00200094))
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#define GPPUDCLK0 ((volatile uint32_t*)(MMIO_BASE+0x00200098))
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#define GPPUDCLK1 ((volatile uint32_t*)(MMIO_BASE+0x0020009C))
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#define GPFSEL0 ((volatile uint32_t*)(mmio_base+0x00200000))
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#define GPFSEL1 ((volatile uint32_t*)(mmio_base+0x00200004))
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#define GPFSEL2 ((volatile uint32_t*)(mmio_base+0x00200008))
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#define GPFSEL3 ((volatile uint32_t*)(mmio_base+0x0020000C))
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#define GPFSEL4 ((volatile uint32_t*)(mmio_base+0x00200010))
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#define GPFSEL5 ((volatile uint32_t*)(mmio_base+0x00200014))
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#define GPSET0 ((volatile uint32_t*)(mmio_base+0x0020001C))
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#define GPSET1 ((volatile uint32_t*)(mmio_base+0x00200020))
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#define GPCLR0 ((volatile uint32_t*)(mmio_base+0x00200028))
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#define GPLEV0 ((volatile uint32_t*)(mmio_base+0x00200034))
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#define GPLEV1 ((volatile uint32_t*)(mmio_base+0x00200038))
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#define GPEDS0 ((volatile uint32_t*)(mmio_base+0x00200040))
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#define GPEDS1 ((volatile uint32_t*)(mmio_base+0x00200044))
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#define GPHEN0 ((volatile uint32_t*)(mmio_base+0x00200064))
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#define GPHEN1 ((volatile uint32_t*)(mmio_base+0x00200068))
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#define GPPUD ((volatile uint32_t*)(mmio_base+0x00200094))
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#define GPPUDCLK0 ((volatile uint32_t*)(mmio_base+0x00200098))
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#define GPPUDCLK1 ((volatile uint32_t*)(mmio_base+0x0020009C))
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#define UART0 0
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#define UART0_DR ((volatile uint32_t*)(MMIO_BASE+0x00201000))
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#define UART0_FR ((volatile uint32_t*)(MMIO_BASE+0x00201018))
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#define UART0_IBRD ((volatile uint32_t*)(MMIO_BASE+0x00201024))
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#define UART0_FBRD ((volatile uint32_t*)(MMIO_BASE+0x00201028))
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#define UART0_LCRH ((volatile uint32_t*)(MMIO_BASE+0x0020102C))
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#define UART0_CR ((volatile uint32_t*)(MMIO_BASE+0x00201030))
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#define UART0_IMSC ((volatile uint32_t*)(MMIO_BASE+0x00201038))
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#define UART0_ICR ((volatile uint32_t*)(MMIO_BASE+0x00201044))
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#define UART0_DR ((volatile uint32_t*)(mmio_base+0x00201000))
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#define UART0_FR ((volatile uint32_t*)(mmio_base+0x00201018))
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#define UART0_IBRD ((volatile uint32_t*)(mmio_base+0x00201024))
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#define UART0_FBRD ((volatile uint32_t*)(mmio_base+0x00201028))
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#define UART0_LCRH ((volatile uint32_t*)(mmio_base+0x0020102C))
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#define UART0_CR ((volatile uint32_t*)(mmio_base+0x00201030))
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#define UART0_IMSC ((volatile uint32_t*)(mmio_base+0x00201038))
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#define UART0_ICR ((volatile uint32_t*)(mmio_base+0x00201044))
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#define UART1 1
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#define AUX_ENABLE ((volatile uint32_t*)(MMIO_BASE+0x00215004))
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#define AUX_MU_IO ((volatile uint32_t*)(MMIO_BASE+0x00215040))
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#define AUX_MU_IER ((volatile uint32_t*)(MMIO_BASE+0x00215044))
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#define AUX_MU_IIR ((volatile uint32_t*)(MMIO_BASE+0x00215048))
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#define AUX_MU_LCR ((volatile uint32_t*)(MMIO_BASE+0x0021504C))
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#define AUX_MU_MCR ((volatile uint32_t*)(MMIO_BASE+0x00215050))
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#define AUX_MU_LSR ((volatile uint32_t*)(MMIO_BASE+0x00215054))
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#define AUX_MU_MSR ((volatile uint32_t*)(MMIO_BASE+0x00215058))
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#define AUX_MU_SCRATCH ((volatile uint32_t*)(MMIO_BASE+0x0021505C))
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#define AUX_MU_CNTL ((volatile uint32_t*)(MMIO_BASE+0x00215060))
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#define AUX_MU_STAT ((volatile uint32_t*)(MMIO_BASE+0x00215064))
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#define AUX_MU_BAUD ((volatile uint32_t*)(MMIO_BASE+0x00215068))
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#define AUX_ENABLE ((volatile uint32_t*)(mmio_base+0x00215004))
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#define AUX_MU_IO ((volatile uint32_t*)(mmio_base+0x00215040))
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#define AUX_MU_IER ((volatile uint32_t*)(mmio_base+0x00215044))
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#define AUX_MU_IIR ((volatile uint32_t*)(mmio_base+0x00215048))
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#define AUX_MU_LCR ((volatile uint32_t*)(mmio_base+0x0021504C))
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#define AUX_MU_MCR ((volatile uint32_t*)(mmio_base+0x00215050))
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#define AUX_MU_LSR ((volatile uint32_t*)(mmio_base+0x00215054))
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#define AUX_MU_MSR ((volatile uint32_t*)(mmio_base+0x00215058))
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#define AUX_MU_SCRATCH ((volatile uint32_t*)(mmio_base+0x0021505C))
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#define AUX_MU_CNTL ((volatile uint32_t*)(mmio_base+0x00215060))
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#define AUX_MU_STAT ((volatile uint32_t*)(mmio_base+0x00215064))
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#define AUX_MU_BAUD ((volatile uint32_t*)(mmio_base+0x00215068))
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/* timing stuff */
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uint64_t cntfrq;
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@ -262,7 +262,7 @@ void uart_exc(uint64_t idx, uint64_t esr, uint64_t elr, uint64_t spsr, uint64_t
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*PM_RTSC = PM_WDOG_MAGIC | PM_RTSC_FULLRST;
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while(1);
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}
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#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880)
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#define VIDEOCORE_MBOX (mmio_base+0x0000B880)
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#define MBOX_READ ((volatile uint32_t*)(VIDEOCORE_MBOX+0x0))
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#define MBOX_POLL ((volatile uint32_t*)(VIDEOCORE_MBOX+0x10))
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#define MBOX_SENDER ((volatile uint32_t*)(VIDEOCORE_MBOX+0x14))
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@ -323,23 +323,23 @@ int hex2bin(unsigned char *s, int n){ int r=0;while(n-->0){r<<=4;
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#endif
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/* sdcard */
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#define EMMC_ARG2 ((volatile uint32_t*)(MMIO_BASE+0x00300000))
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#define EMMC_BLKSIZECNT ((volatile uint32_t*)(MMIO_BASE+0x00300004))
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#define EMMC_ARG1 ((volatile uint32_t*)(MMIO_BASE+0x00300008))
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#define EMMC_CMDTM ((volatile uint32_t*)(MMIO_BASE+0x0030000C))
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#define EMMC_RESP0 ((volatile uint32_t*)(MMIO_BASE+0x00300010))
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#define EMMC_RESP1 ((volatile uint32_t*)(MMIO_BASE+0x00300014))
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#define EMMC_RESP2 ((volatile uint32_t*)(MMIO_BASE+0x00300018))
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#define EMMC_RESP3 ((volatile uint32_t*)(MMIO_BASE+0x0030001C))
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#define EMMC_DATA ((volatile uint32_t*)(MMIO_BASE+0x00300020))
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#define EMMC_STATUS ((volatile uint32_t*)(MMIO_BASE+0x00300024))
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#define EMMC_CONTROL0 ((volatile uint32_t*)(MMIO_BASE+0x00300028))
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#define EMMC_CONTROL1 ((volatile uint32_t*)(MMIO_BASE+0x0030002C))
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#define EMMC_INTERRUPT ((volatile uint32_t*)(MMIO_BASE+0x00300030))
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#define EMMC_INT_MASK ((volatile uint32_t*)(MMIO_BASE+0x00300034))
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#define EMMC_INT_EN ((volatile uint32_t*)(MMIO_BASE+0x00300038))
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#define EMMC_CONTROL2 ((volatile uint32_t*)(MMIO_BASE+0x0030003C))
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#define EMMC_SLOTISR_VER ((volatile uint32_t*)(MMIO_BASE+0x003000FC))
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#define EMMC_ARG2 ((volatile uint32_t*)(mmio_base+0x00300000))
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#define EMMC_BLKSIZECNT ((volatile uint32_t*)(mmio_base+0x00300004))
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#define EMMC_ARG1 ((volatile uint32_t*)(mmio_base+0x00300008))
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#define EMMC_CMDTM ((volatile uint32_t*)(mmio_base+0x0030000C))
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#define EMMC_RESP0 ((volatile uint32_t*)(mmio_base+0x00300010))
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#define EMMC_RESP1 ((volatile uint32_t*)(mmio_base+0x00300014))
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#define EMMC_RESP2 ((volatile uint32_t*)(mmio_base+0x00300018))
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#define EMMC_RESP3 ((volatile uint32_t*)(mmio_base+0x0030001C))
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#define EMMC_DATA ((volatile uint32_t*)(mmio_base+0x00300020))
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#define EMMC_STATUS ((volatile uint32_t*)(mmio_base+0x00300024))
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#define EMMC_CONTROL0 ((volatile uint32_t*)(mmio_base+0x00300028))
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#define EMMC_CONTROL1 ((volatile uint32_t*)(mmio_base+0x0030002C))
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#define EMMC_INTERRUPT ((volatile uint32_t*)(mmio_base+0x00300030))
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#define EMMC_INT_MASK ((volatile uint32_t*)(mmio_base+0x00300034))
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#define EMMC_INT_EN ((volatile uint32_t*)(mmio_base+0x00300038))
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#define EMMC_CONTROL2 ((volatile uint32_t*)(mmio_base+0x0030003C))
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#define EMMC_SLOTISR_VER ((volatile uint32_t*)(mmio_base+0x003000FC))
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// command flags
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#define CMD_NEED_APP 0x80000000
|
||||
|
|
@ -1112,6 +1112,13 @@ int bootboot_main(uint64_t hcl)
|
|||
volatile bpb_t *bpb;
|
||||
MMapEnt *mmap;
|
||||
|
||||
/* first things first, get the base address */
|
||||
asm volatile ("mrs %0, midr_el1" : "=r" (reg));
|
||||
switch(reg&0xFFF0) {
|
||||
case 0xD030: mmio_base = 0x3F000000; break; /* Raspberry Pi 3 */
|
||||
default: mmio_base = 0xFE000000; break; /* Raspberry Pi 4 */
|
||||
}
|
||||
|
||||
/* initialize UART */
|
||||
*UART0_CR = 0; // turn off UART0
|
||||
*AUX_ENABLE = 0; // turn off UART1
|
||||
|
|
@ -1168,7 +1175,7 @@ int bootboot_main(uint64_t hcl)
|
|||
bootboot->protocol = PROTOCOL_STATIC | LOADER_RPI;
|
||||
bootboot->size = 128;
|
||||
bootboot->numcores = 4;
|
||||
bootboot->arch.aarch64.mmio_ptr = MMIO_BASE;
|
||||
bootboot->arch.aarch64.mmio_ptr = mmio_base;
|
||||
// set up a framebuffer so that we can write on screen
|
||||
if(!GetLFB(0, 0)) goto viderr;
|
||||
puts("Booting OS...\n");
|
||||
|
|
@ -1567,7 +1574,7 @@ gzerr: puts("BOOTBOOT-PANIC: Unable to uncompress\n");
|
|||
mmap++; bootboot->size+=sizeof(MMapEnt);
|
||||
|
||||
// MMIO area
|
||||
mmap->ptr=MMIO_BASE; mmap->size=((uint64_t)0x40200000-MMIO_BASE) | MMAP_MMIO;
|
||||
mmap->ptr=mmio_base; mmap->size=((uint64_t)0x40200000-mmio_base) | MMAP_MMIO;
|
||||
mmap++; bootboot->size+=sizeof(MMapEnt);
|
||||
|
||||
#if MEM_DEBUG
|
||||
|
|
@ -1619,7 +1626,7 @@ viderr:
|
|||
paging[2*512]=(uint64_t)((uint8_t*)&__paging+3*PAGESIZE)|0b11|(3<<8)|(1<<10); //AF=1,Block=1,Present=1
|
||||
// identity L2 2M blocks
|
||||
mp>>=21;
|
||||
np=MMIO_BASE>>21;
|
||||
np=mmio_base>>21;
|
||||
for(r=1;r<512;r++)
|
||||
paging[2*512+r]=(uint64_t)(((uint64_t)r<<21))|0b01|(1<<10)|(r>=np?(2<<8)|(1<<2)|(1L<<54):(3<<8)); //device SH=2 OSH
|
||||
// identity L3
|
||||
|
|
@ -1630,7 +1637,7 @@ viderr:
|
|||
// core L2
|
||||
// map MMIO in kernel space
|
||||
for(r=0;r<32;r++)
|
||||
paging[4*512+448+r]=(uint64_t)(MMIO_BASE+((uint64_t)r<<21))|0b01|(2<<8)|(1<<10)|(1<<2)|(1L<<54); //OSH, Attr=1, NX
|
||||
paging[4*512+448+r]=(uint64_t)(mmio_base+((uint64_t)r<<21))|0b01|(2<<8)|(1<<10)|(1<<2)|(1L<<54); //OSH, Attr=1, NX
|
||||
// map framebuffer
|
||||
for(r=0;r<16;r++)
|
||||
paging[4*512+480+r]=(uint64_t)((uint8_t*)&__paging+(6+r)*PAGESIZE)|0b11|(2<<8)|(1<<10)|(2<<2)|(1L<<54); //OSH, Attr=2
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ int main(int argc, char** argv)
|
|||
if(argc < 2) {
|
||||
printf( "BOOTBOOT mkboot utility - bztsrc@gitlab\n\nUsage:\n"
|
||||
" ./mkboot <disk>\n\n"
|
||||
"Maps GPT EFI System Partition into MBR so that Raspberry Pi 3\n"
|
||||
"Maps GPT EFI System Partition into MBR so that Raspberry Pi\n"
|
||||
"firmware can find it's files and boot from it.\n"
|
||||
"Examples:\n"
|
||||
" ./mkboot diskimage.dd - modify a disk image file\n"
|
||||
|
|
|
|||
BIN
boot.bin
BIN
boot.bin
Binary file not shown.
BIN
bootboot.img
BIN
bootboot.img
Binary file not shown.
Binary file not shown.
|
|
@ -3,7 +3,7 @@ BOOTBOOT Minta Bootolható Lemezkép Fájlok
|
|||
|
||||
Általános leírásért lásd a [BOOTBOOT Protokoll](https://gitlab.com/bztsrc/bootboot)t.
|
||||
|
||||
- disk-rpi.img.gz: minta lemezkép AArch64-hez RaspberryPi 3-on
|
||||
- disk-rpi.img.gz: minta lemezkép AArch64-hez RaspberryPi 3-on és 4-en
|
||||
- disk-x86.img.gz: minta lemezkép x86_64-hez (CDROM, BIOS, UEFI)
|
||||
- initrd.rom.gz: minta initrd ROM kép (beágyazott BIOS rendszerekhez)
|
||||
- mkimg.c: egy nagyon szimpla és egyszerű lemezkép készítő
|
||||
|
|
@ -28,7 +28,7 @@ A `make all` parancsot futtatva a következő fájlokat hozza létre:
|
|||
A disk-x86.img egy speciális hibrid lemezkép, amit átnevezhetsz disk-x86.iso-ra és kiégetheted egy CDROM-ra; vagy bebootolhatod
|
||||
USB pendrávjról is BIOS valamint UEFI gépeken egyaránt.
|
||||
|
||||
A disk-rpi.img egy (Class 10) SD kártyára írható, és Raspberry Pi 3-on bootolható.
|
||||
A disk-rpi.img egy (Class 10) SD kártyára írható, és Raspberry Pi 3-on és 4-en bootolható.
|
||||
|
||||
A lemezképekben mindössze egy boot partíció található. Az `fdisk` paranccsal szabadon hozzáadhatsz még partíciókat az izlésednek
|
||||
megfelelően.
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ BOOTBOOT Example Bootable Disk Images
|
|||
|
||||
See [BOOTBOOT Protocol](https://gitlab.com/bztsrc/bootboot) for common details.
|
||||
|
||||
- disk-rpi.img.gz: an example image for AArch64 and RaspberryPi 3
|
||||
- disk-rpi.img.gz: an example image for AArch64 and RaspberryPi 3 and 4
|
||||
- disk-x86.img.gz: an example image for x86_64 (CDROM, BIOS, UEFI)
|
||||
- initrd.rom.gz: an example initrd ROM image (for embedded BIOS systems)
|
||||
- mkimg.c: is a very simple bootable disk image creator tool
|
||||
|
|
@ -28,7 +28,7 @@ Executing `make all` will create the following files:
|
|||
The disk-x86.img is a special hybrid image, which can be renamed to disk-x86.iso and then burnt to a CDROM; it can also be
|
||||
booted from an USB stick in a BIOS machine as well as an UEFI machine.
|
||||
|
||||
The disk-rpi.img can be written to an SDCard (Class 10) and booted on a Raspberry Pi 3.
|
||||
The disk-rpi.img can be written to an SDCard (Class 10) and booted on a Raspberry Pi 3 and 4.
|
||||
|
||||
The disk images contain only one boot partition. Feel free to use `fdisk` and add more partitions to your needs.
|
||||
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -363,7 +363,7 @@ int createdisk(int disksize, char *diskname)
|
|||
/* README.TXT */
|
||||
iso[8260]=0x22+12; /* recordsize */
|
||||
setinte(21, &iso[8262]); /* LBA */
|
||||
setinte(129, &iso[8270]); /* size */
|
||||
setinte(130, &iso[8270]); /* size */
|
||||
iso[8278]=ts->tm_year; /* date */
|
||||
iso[8279]=ts->tm_mon+1;
|
||||
iso[8280]=ts->tm_mday;
|
||||
|
|
@ -379,7 +379,7 @@ int createdisk(int disksize, char *diskname)
|
|||
memcpy(&iso[10240], "BOOTBOOT Live Image\r\n\r\nBootable as\r\n"
|
||||
" - CDROM (El Torito, UEFI)\r\n"
|
||||
" - USB stick (BIOS, Multiboot, UEFI)\r\n"
|
||||
" - SD card (Raspberry Pi 3)", 129);
|
||||
" - SD card (Raspberry Pi 3+)", 130);
|
||||
|
||||
f=fopen(diskname,"wb");
|
||||
if(!f) {
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ bootboot_record:
|
|||
db 05Ah-($-$$) dup 0
|
||||
.skipid: ;relocate our code to offset 0h:600h
|
||||
cli
|
||||
cld
|
||||
xor ax, ax
|
||||
mov ss, ax
|
||||
mov sp, 600h
|
||||
|
|
@ -89,7 +90,6 @@ bootboot_record:
|
|||
call .getaddr
|
||||
.getaddr: pop si
|
||||
sub si, .getaddr-bootboot_record
|
||||
cld
|
||||
mov di, sp
|
||||
;clear data area 500h-600h
|
||||
sub di, 100h
|
||||
|
|
|
|||
Loading…
Reference in a new issue