2012-03-17 10:18:03 -04:00
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/*******************************************************************************
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2013-07-10 09:26:01 -04:00
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Copyright(C) Jonas 'Sortie' Termansen 2011, 2012.
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2012-03-17 10:18:03 -04:00
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2013-07-10 09:26:01 -04:00
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This file is part of Sortix.
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2012-03-17 10:18:03 -04:00
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2013-07-10 09:26:01 -04:00
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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2012-03-17 10:18:03 -04:00
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2013-07-10 09:26:01 -04:00
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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2012-03-17 10:18:03 -04:00
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2013-07-10 09:26:01 -04:00
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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2012-03-17 10:18:03 -04:00
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2013-07-10 09:26:01 -04:00
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com.cpp
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Handles communication to COM serial ports.
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2012-03-17 10:18:03 -04:00
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*******************************************************************************/
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2012-03-21 19:52:29 -04:00
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#include <sortix/kernel/platform.h>
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2012-08-01 11:30:34 -04:00
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#include <sortix/kernel/kthread.h>
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2012-08-07 18:19:44 -04:00
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#include <sortix/kernel/refcount.h>
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#include <sortix/kernel/ioctx.h>
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#include <sortix/kernel/inode.h>
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#include <sortix/kernel/descriptor.h>
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#include <sortix/kernel/interlock.h>
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2013-01-09 17:30:36 -05:00
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#include <sortix/kernel/interrupt.h>
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2013-05-12 18:41:30 -04:00
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#include <sortix/kernel/process.h>
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#include <sortix/kernel/thread.h>
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2013-01-09 17:30:36 -05:00
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2012-08-07 18:19:44 -04:00
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#include <sortix/stat.h>
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2013-01-09 17:30:36 -05:00
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2012-09-22 10:44:50 -04:00
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#include <errno.h>
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2013-01-09 17:30:36 -05:00
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2012-03-17 10:18:03 -04:00
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#include "com.h"
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namespace Sortix {
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namespace COM {
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// It appears this code is unable to get interrupts working correctly. Somehow
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// we don't get interrupts upon receiving data, at least under VirtualBox. This
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// hack changes the code such that it polls occasionally instead. Hopefully this
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// won't cause data loss, but I suspect that it will.
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// TODO: It appears that this code causes kernel instability, possibly due to
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// the broken way blocking system calls are implemented in Sortix.
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#define POLL_HACK 1
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// Another alternative is to use the polling code in a completely blocking
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// manner. While this may give nicer transfer speeds and less data loss, it
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// locks up the whole system.
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#define POLL_BLOCKING 0
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// Yet another alternative is to use POLL_HACK, but return EGAIN and let user-
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// space call retry, rather than relying on the broken syscall interstructure.
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#define POLL_EAGAIN 1
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2012-08-07 18:19:44 -04:00
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#if !POLL_EAGAIN && !POLL_HACK
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2012-08-01 11:30:34 -04:00
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#error The interrupt-based code was broken in the kthread branch.
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#error You need to port this to the new thread/interrupt API.
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#warning Oh, and fix the above mentioned bugs too.
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#endif
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2012-03-17 10:18:03 -04:00
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const uint16_t TXR = 0; // Transmit register
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const uint16_t RXR = 0; // Receive register
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const uint16_t IER = 1; // Interrupt Enable
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const uint16_t IIR = 2; // Interrupt ID
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const uint16_t FCR = 2; // FIFO control
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const uint16_t LCR = 3; // Line control
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const uint16_t MCR = 4; // Modem control
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const uint16_t LSR = 5; // Line Status
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const uint16_t MSR = 6; // Modem Status
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const uint16_t SCR = 7; // Scratch Register
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const uint16_t DLL = 0; // Divisor Latch Low
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const uint16_t DLM = 1; // Divisor latch High
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const uint8_t LCR_DLAB = 0x80; // Divisor latch access bit
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const uint8_t LCR_SBC = 0x40; // Set break control
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const uint8_t LCR_SPAR = 0x20; // Stick parity (?)
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const uint8_t LCR_EPAR = 0x10; // Even parity select
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const uint8_t LCR_PARITY = 0x08; // Parity Enable
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const uint8_t LCR_STOP = 0x04; // Stop bits: 0=1 bit, 1=2 bits
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const uint8_t LCR_WLEN5 = 0x00; // Wordlength: 5 bits
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const uint8_t LCR_WLEN6 = 0x01; // Wordlength: 6 bits
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const uint8_t LCR_WLEN7 = 0x02; // Wordlength: 7 bits
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const uint8_t LCR_WLEN8 = 0x03; // Wordlength: 8 bits
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const uint8_t LSR_TEMT = 0x40; // Transmitter empty
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const uint8_t LSR_THRE = 0x20; // Transmit-hold-register empty
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const uint8_t LSR_READY = 0x1; // Data received
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const uint8_t LSR_BOTH_EMPTY = LSR_TEMT | LSR_THRE;
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const uint8_t IIR_NO_INTERRUPT = (1U<<0U);
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const uint8_t IIR_INTERRUPT_TYPE = ((1U<<1U) | (1U<<2U) | (1U<<3U));
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const uint8_t IIR_TIMEOUT = ((1U<<2U) | (1U<<3U));
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const uint8_t IIR_RECV_LINE_STATUS = ((1U<<1U) | (1U<<2U));
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const uint8_t IIR_RECV_DATA = (1U<<2U);
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const uint8_t IIR_SENT_DATA = (1U<<1U);
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const uint8_t IIR_MODEM_STATUS = 0;
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const uint8_t IER_DATA = (1U<<0U);
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const uint8_t IER_SENT = (1U<<1U);
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const uint8_t IER_LINE_STATUS = (1U<<2U);
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const uint8_t IER_MODEM_STATUS = (1U<<3U);
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const uint8_t IER_SLEEP_MODE = (1U<<4U);
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const uint8_t IER_LOW_POWER = (1U<<5U);
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const unsigned BASE_BAUD = 1843200/16;
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const unsigned UART8250 = 1;
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const unsigned UART16450 = 2;
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const unsigned UART16550 = 3;
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const unsigned UART16550A = 4;
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const unsigned UART16750 = 5;
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const size_t NUMCOMPORTS = 4;
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// The IO base ports of each COM port.
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static uint16_t comports[1+NUMCOMPORTS];
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// The results of running HardwareProbe on each COM port.
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unsigned hwversion[1+NUMCOMPORTS];
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// Uses various characteristics of the UART chips to determine the hardware.
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static unsigned HardwareProbe(uint16_t port)
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{
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// Set the value "0xE7" to the FCR to test the status of the FIFO flags.
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CPU::OutPortB(port + FCR, 0xE7);
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uint8_t iir = CPU::InPortB(port + IIR);
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if ( iir & (1U<<6U) )
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{
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if ( iir & (1<<7U) )
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{
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return (iir & (1U<<5U)) ? UART16750 : UART16550A;
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}
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return UART16550;
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}
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// See if the scratch register returns what we write into it. The 8520
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// doesn't do it. This is technically undefined behavior, but it is useful
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// to detect hardware versions.
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uint16_t anyvalue = 0x2A;
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CPU::OutPortB(port + SCR, anyvalue);
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return CPU::InPortB(port + SCR) == anyvalue ? UART16450 : UART8250;
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}
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static inline void WaitForEmptyBuffers(uint16_t port)
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{
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while ( (CPU::InPortB(port + LSR) & LSR_BOTH_EMPTY) != LSR_BOTH_EMPTY ) { }
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}
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static inline bool IsLineReady(uint16_t port)
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{
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return CPU::InPortB(port + LSR) & LSR_READY;
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}
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static inline bool CanWriteByte(uint16_t port)
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{
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return CPU::InPortB(port + LSR) & LSR_THRE;
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}
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ssize_t ReadBlocking(uint16_t port, void* buf, size_t size)
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{
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if ( SSIZE_MAX < size ) { size = SSIZE_MAX; }
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uint8_t* buffer = (uint8_t*) buf;
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uint8_t interruptsenabled = CPU::InPortB(port + IER);
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CPU::OutPortB(port + IER, 0);
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for ( size_t i = 0; i < size; i++ )
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{
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while ( !IsLineReady(port) ) { }
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buffer[i] = CPU::InPortB(port + RXR);
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}
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WaitForEmptyBuffers(port);
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CPU::OutPortB(port + IER, interruptsenabled);
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return size;
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}
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ssize_t WriteBlocking(uint16_t port, const void* buf, size_t size)
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{
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if ( SSIZE_MAX < size ) { size = SSIZE_MAX; }
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const uint8_t* buffer = (const uint8_t*) buf;
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uint8_t interruptsenabled = CPU::InPortB(port + IER);
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CPU::OutPortB(port + IER, 0);
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for ( size_t i = 0; i < size; i++ )
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{
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while ( !CanWriteByte(port) ) { }
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CPU::OutPortB(port + TXR, buffer[i]);
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}
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WaitForEmptyBuffers(port);
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CPU::OutPortB(port + IER, interruptsenabled);
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return size;
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}
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void EarlyInit()
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{
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// We can fetch COM port information from the BIOS Data Area.
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volatile uint16_t* const bioscomports = (uint16_t* const) 0x0400UL;
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for ( size_t i = 1; i <= NUMCOMPORTS; i++ )
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{
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comports[i] = bioscomports[i-1];
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if ( !comports[i] ) { continue; }
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hwversion[i] = HardwareProbe(comports[i]);
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CPU::OutPortB(comports[i] + IER, 0x0);
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}
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}
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2012-08-07 18:19:44 -04:00
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class DevCOMPort : public AbstractInode
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2012-03-17 10:18:03 -04:00
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{
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public:
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2012-08-07 18:19:44 -04:00
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DevCOMPort(dev_t dev, uid_t owner, gid_t group, mode_t mode, uint16_t port);
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2012-03-17 10:18:03 -04:00
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virtual ~DevCOMPort();
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2012-08-07 18:19:44 -04:00
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virtual int sync(ioctx_t* ctx);
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virtual ssize_t read(ioctx_t* ctx, uint8_t* buf, size_t count);
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virtual ssize_t write(ioctx_t* ctx, const uint8_t* buf, size_t count);
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2012-03-17 10:18:03 -04:00
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public:
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void OnInterrupt();
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private:
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2012-08-01 11:30:34 -04:00
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kthread_mutex_t portlock;
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2012-08-07 18:19:44 -04:00
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uint16_t port;
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2012-03-17 10:18:03 -04:00
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};
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2012-08-07 18:19:44 -04:00
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DevCOMPort::DevCOMPort(dev_t dev, uid_t owner, gid_t group, mode_t mode,
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uint16_t port)
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2012-03-17 10:18:03 -04:00
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{
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2012-08-07 18:19:44 -04:00
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inode_type = INODE_TYPE_STREAM;
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2012-03-17 10:18:03 -04:00
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this->port = port;
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2012-08-01 11:30:34 -04:00
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this->portlock = KTHREAD_MUTEX_INITIALIZER;
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2012-08-07 18:19:44 -04:00
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this->stat_uid = owner;
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this->stat_gid = group;
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this->type = S_IFCHR;
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this->stat_mode = (mode & S_SETABLE) | this->type;
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this->dev = dev;
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this->ino = (ino_t) this;
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2012-03-17 10:18:03 -04:00
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}
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DevCOMPort::~DevCOMPort()
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{
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}
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2012-08-07 18:19:44 -04:00
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int DevCOMPort::sync(ioctx_t* /*ctx*/)
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{
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// TODO: Not implemented yet, please wait for all outstanding requests.
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return 0;
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}
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2012-03-17 10:18:03 -04:00
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#if POLL_HACK
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2012-08-07 18:19:44 -04:00
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ssize_t DevCOMPort::read(ioctx_t* ctx, uint8_t* dest, size_t count)
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2012-03-17 10:18:03 -04:00
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{
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if ( !count ) { return 0; }
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if ( SSIZE_MAX < count ) { count = SSIZE_MAX; }
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2012-08-01 11:30:34 -04:00
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ScopedLock lock(&portlock);
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2012-03-17 10:18:03 -04:00
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2012-08-01 11:30:34 -04:00
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while ( !(CPU::InPortB(port + LSR) & LSR_READY) )
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if ( Signal::IsPending() )
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{
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errno = EINTR;
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2012-08-01 11:30:34 -04:00
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return -1;
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}
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2012-03-17 10:18:03 -04:00
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size_t sofar = 0;
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do
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{
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if ( count <= sofar ) { break; }
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2012-08-07 18:19:44 -04:00
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uint8_t val = CPU::InPortB(port + RXR);
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if ( !ctx->copy_to_dest(dest + sofar++, &val, sizeof(val)) )
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return -1;
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2012-03-17 10:18:03 -04:00
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} while ( CPU::InPortB(port + LSR) & LSR_READY);
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return sofar;
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}
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2012-08-07 18:19:44 -04:00
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ssize_t DevCOMPort::write(ioctx_t* ctx, const uint8_t* src, size_t count)
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2012-03-17 10:18:03 -04:00
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{
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if ( !count ) { return 0; }
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if ( SSIZE_MAX < count ) { count = SSIZE_MAX; };
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2012-08-01 11:30:34 -04:00
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ScopedLock lock(&portlock);
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while ( !(CPU::InPortB(port + LSR) & LSR_THRE) )
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if ( Signal::IsPending() )
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{
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errno = EINTR;
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2012-08-01 11:30:34 -04:00
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return -1;
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}
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2012-03-17 10:18:03 -04:00
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size_t sofar = 0;
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do
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{
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if ( count <= sofar ) { break; }
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2012-08-07 18:19:44 -04:00
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uint8_t val;
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if ( !ctx->copy_from_src(&val, src + sofar++, sizeof(val)) )
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return -1;
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CPU::OutPortB(port + TXR, val);
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2012-03-17 10:18:03 -04:00
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} while ( CPU::InPortB(port + LSR) & LSR_THRE );
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|
|
|
|
|
return sofar;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
2012-08-07 18:19:44 -04:00
|
|
|
#error Yeah, please port these to the new IO interface.
|
|
|
|
|
|
|
|
ssize_t DevCOMPort::Read(byte* dest, size_t count)
|
2012-03-17 10:18:03 -04:00
|
|
|
{
|
|
|
|
if ( !count ) { return 0; }
|
|
|
|
if ( SSIZE_MAX < count ) { count = SSIZE_MAX; }
|
|
|
|
#if POLL_BLOCKING
|
|
|
|
return ReadBlocking(port, dest, 1);
|
|
|
|
#endif
|
|
|
|
uint8_t lsr = CPU::InPortB(port + LSR);
|
|
|
|
if ( !(lsr & LSR_READY) )
|
|
|
|
{
|
2012-08-01 11:30:34 -04:00
|
|
|
Panic("Can't wait for com data receive event");
|
2012-08-07 18:19:44 -04:00
|
|
|
Error::Set(EBLOCKING);
|
2012-03-17 10:18:03 -04:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
size_t sofar = 0;
|
|
|
|
do
|
|
|
|
{
|
|
|
|
if ( count <= sofar ) { break; }
|
|
|
|
dest[sofar++] = CPU::InPortB(port + RXR);
|
|
|
|
} while ( CPU::InPortB(port + LSR) & LSR_READY);
|
|
|
|
|
|
|
|
return sofar;
|
|
|
|
}
|
|
|
|
|
2012-09-21 13:25:22 -04:00
|
|
|
ssize_t DevCOMPort::Write(const uint8_t* src, size_t count)
|
2012-03-17 10:18:03 -04:00
|
|
|
{
|
|
|
|
if ( !count ) { return 0; }
|
|
|
|
if ( SSIZE_MAX < count ) { count = SSIZE_MAX; };
|
|
|
|
#if POLL_BLOCKING
|
|
|
|
return WriteBlocking(port, src, 1);
|
|
|
|
#endif
|
|
|
|
uint8_t lsr = CPU::InPortB(port + LSR);
|
|
|
|
if ( !(lsr & LSR_THRE) )
|
|
|
|
{
|
2012-08-01 11:30:34 -04:00
|
|
|
Panic("Can't wait for com data sent event");
|
2012-08-07 18:19:44 -04:00
|
|
|
Error::Set(EBLOCKING);
|
2012-03-17 10:18:03 -04:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
size_t sofar = 0;
|
|
|
|
do
|
|
|
|
{
|
|
|
|
if ( count <= sofar ) { break; }
|
|
|
|
CPU::OutPortB(port + TXR, src[sofar++]);
|
|
|
|
} while ( CPU::InPortB(port + LSR) & LSR_THRE );
|
|
|
|
|
|
|
|
return sofar;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
void DevCOMPort::OnInterrupt()
|
|
|
|
{
|
|
|
|
#if POLL_HACK || POLL_BLOCKING
|
|
|
|
return;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
uint8_t iir = CPU::InPortB(port + IIR);
|
|
|
|
if ( iir & IIR_NO_INTERRUPT ) { return; }
|
|
|
|
uint8_t intrtype = iir & IIR_INTERRUPT_TYPE;
|
|
|
|
switch ( intrtype )
|
|
|
|
{
|
|
|
|
case IIR_TIMEOUT:
|
|
|
|
CPU::InPortB(port + RXR);
|
|
|
|
break;
|
|
|
|
case IIR_RECV_LINE_STATUS:
|
|
|
|
// TODO: Proper error handling!
|
|
|
|
CPU::InPortB(port + LSR);
|
|
|
|
break;
|
|
|
|
case IIR_RECV_DATA:
|
2012-08-01 11:30:34 -04:00
|
|
|
Panic("Can't wait for com data sent event");
|
2012-03-17 10:18:03 -04:00
|
|
|
break;
|
|
|
|
case IIR_SENT_DATA:
|
2012-08-01 11:30:34 -04:00
|
|
|
Panic("Can't wait for com data sent event");
|
2012-03-17 10:18:03 -04:00
|
|
|
CPU::InPortB(port + IIR);
|
|
|
|
break;
|
|
|
|
case IIR_MODEM_STATUS:
|
|
|
|
CPU::InPortB(port + MSR);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-07 18:19:44 -04:00
|
|
|
Ref<DevCOMPort> comdevices[1+NUMCOMPORTS];
|
2012-03-17 10:18:03 -04:00
|
|
|
|
|
|
|
static void UARTIRQHandler(CPU::InterruptRegisters* /*regs*/, void* /*user*/)
|
|
|
|
{
|
|
|
|
for ( size_t i = 1; i <= NUMCOMPORTS; i++ )
|
|
|
|
{
|
|
|
|
if ( !comdevices[i] ) { continue; }
|
|
|
|
comdevices[i]->OnInterrupt();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-07 18:19:44 -04:00
|
|
|
void Init(const char* devpath, Ref<Descriptor> slashdev)
|
2012-03-17 10:18:03 -04:00
|
|
|
{
|
2012-08-07 18:19:44 -04:00
|
|
|
ioctx_t ctx; SetupKernelIOCtx(&ctx);
|
2012-03-17 10:18:03 -04:00
|
|
|
for ( size_t i = 1; i <= NUMCOMPORTS; i++ )
|
|
|
|
{
|
2012-08-07 18:19:44 -04:00
|
|
|
if ( !comports[i] ) { comdevices[i] = Ref<DevCOMPort>(); continue; }
|
|
|
|
comdevices[i] = Ref<DevCOMPort>
|
|
|
|
(new DevCOMPort(slashdev->dev, 0, 0, 0660, comports[i]));
|
2012-03-17 10:18:03 -04:00
|
|
|
if ( !comdevices[i] )
|
|
|
|
{
|
|
|
|
PanicF("Unable to allocate device for COM port %zu at 0x%x", i,
|
|
|
|
comports[i]);
|
|
|
|
}
|
|
|
|
char name[5] = "comN";
|
|
|
|
name[3] = '0' + i;
|
2012-08-07 18:19:44 -04:00
|
|
|
if ( LinkInodeInDir(&ctx, slashdev, name, comdevices[i]) != 0 )
|
|
|
|
PanicF("Unable to link %s/%s to COM port driver.", devpath, name);
|
2012-03-17 10:18:03 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
Interrupt::RegisterHandler(Interrupt::IRQ3, UARTIRQHandler, NULL);
|
|
|
|
Interrupt::RegisterHandler(Interrupt::IRQ4, UARTIRQHandler, NULL);
|
|
|
|
|
|
|
|
// Initialize the ports so we can transfer data.
|
|
|
|
for ( size_t i = 1; i <= NUMCOMPORTS; i++ )
|
|
|
|
{
|
|
|
|
uint16_t port = comports[i];
|
|
|
|
if ( !port ) { continue; }
|
|
|
|
#if POLL_HACK || POLL_BLOCKING
|
|
|
|
uint8_t interrupts = 0;
|
|
|
|
#else
|
|
|
|
uint8_t interrupts = IER_DATA
|
|
|
|
| IER_SENT
|
|
|
|
| IER_LINE_STATUS
|
|
|
|
| IER_MODEM_STATUS;
|
|
|
|
#endif
|
|
|
|
CPU::OutPortB(port + FCR, 0);
|
|
|
|
CPU::OutPortB(port + LCR, 0x80);
|
|
|
|
CPU::OutPortB(port + DLL, 0xC);
|
|
|
|
CPU::OutPortB(port + DLM, 0x0);
|
|
|
|
CPU::OutPortB(port + LCR, 0x3); // 8n1
|
|
|
|
CPU::OutPortB(port + MCR, 0x3); // DTR + RTS
|
|
|
|
CPU::OutPortB(port + IER, interrupts);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace COM
|
|
|
|
} // namespace Sortix
|