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https://gitlab.com/sortix/sortix.git
synced 2023-02-13 20:55:38 -05:00
The PIC can now be deprogrammed and reprogrammed.
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parent
a75b215fe3
commit
00869bcdc1
2 changed files with 36 additions and 15 deletions
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@ -87,6 +87,38 @@ const unsigned NUM_INTERRUPTS = 256UL;
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Handler interrupthandlers[NUM_INTERRUPTS];
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Handler interrupthandlers[NUM_INTERRUPTS];
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void* interrupthandlerptr[NUM_INTERRUPTS];
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void* interrupthandlerptr[NUM_INTERRUPTS];
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extern "C" void ReprogramPIC()
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{
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uint8_t mastermask = 0;
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uint8_t slavemask = 0;
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CPU::OutPortB(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, IRQ0);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, IRQ8);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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CPU::OutPortB(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, mastermask);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, slavemask);
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}
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extern "C" void DeprogramPIC()
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{
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uint8_t mastermask = 0;
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uint8_t slavemask = 0;
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CPU::OutPortB(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, 0x08);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, 0x70);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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CPU::OutPortB(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, mastermask);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, slavemask);
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}
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void Init()
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void Init()
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{
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{
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initialized = false;
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initialized = false;
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@ -100,18 +132,7 @@ void Init()
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}
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}
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// Remap the IRQ table on the PICs.
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// Remap the IRQ table on the PICs.
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uint8_t mastermask = 0;
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ReprogramPIC();
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uint8_t slavemask = 0;
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CPU::OutPortB(PIC_MASTER + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_SLAVE + PIC_COMMAND, PIC_CMD_INIT | PIC_ICW1_ICW4);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, IRQ0);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, IRQ8);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, 0x04); // Slave PIC at IRQ2
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, 0x02); // Cascade Identity
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CPU::OutPortB(PIC_MASTER + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, PIC_MODE_8086);
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CPU::OutPortB(PIC_MASTER + PIC_DATA, mastermask);
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CPU::OutPortB(PIC_SLAVE + PIC_DATA, slavemask);
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RegisterRawHandler(0, isr0, false);
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RegisterRawHandler(0, isr0, false);
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RegisterRawHandler(1, isr1, false);
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RegisterRawHandler(1, isr1, false);
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@ -54,7 +54,7 @@ namespace Sortix
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return microsecondssinceboot;
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return microsecondssinceboot;
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}
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}
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void RequestIQR0()
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extern "C" void RequestIRQ0()
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{
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{
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// The value we send to the PIT is the value to divide it's input clock
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// The value we send to the PIT is the value to divide it's input clock
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// (1193180 Hz) by, to get our required frequency. Important to note is
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// (1193180 Hz) by, to get our required frequency. Important to note is
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@ -95,7 +95,7 @@ namespace Sortix
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didUglyIRQ0Hack = false;
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didUglyIRQ0Hack = false;
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RequestIQR0();
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RequestIRQ0();
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}
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}
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void OnIRQ0(CPU::InterruptRegisters* Regs, void* /*user*/)
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void OnIRQ0(CPU::InterruptRegisters* Regs, void* /*user*/)
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@ -114,7 +114,7 @@ namespace Sortix
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// TODO: There is a horrible bug that causes Sortix to only receive
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// TODO: There is a horrible bug that causes Sortix to only receive
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// one IRQ0 on my laptop, but it works in virtual machines. But
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// one IRQ0 on my laptop, but it works in virtual machines. But
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// re-requesting an addtional time seems to work. Hacky and ugly.
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// re-requesting an addtional time seems to work. Hacky and ugly.
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if ( !didUglyIRQ0Hack ) { RequestIQR0(); didUglyIRQ0Hack = true; }
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if ( !didUglyIRQ0Hack ) { RequestIRQ0(); didUglyIRQ0Hack = true; }
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}
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}
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// TODO: Implement all the other useful functions regarding time.
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// TODO: Implement all the other useful functions regarding time.
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