mirror of
https://gitlab.com/sortix/sortix.git
synced 2023-02-13 20:55:38 -05:00
Refactored the PCI code to become a library of utility functions.
This commit is contained in:
Jonas 'Sortie' Termansen
parent
5f6ca5e729
commit
19b5451f3b
4 changed files with 244 additions and 307 deletions
75
sortix/include/sortix/kernel/pci.h
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75
sortix/include/sortix/kernel/pci.h
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@ -0,0 +1,75 @@
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/*******************************************************************************
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Copyright(C) Jonas 'Sortie' Termansen 2011, 2012.
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This file is part of Sortix.
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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pci.h
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Functions for handling PCI devices.
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*******************************************************************************/
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#ifndef SORTIX_PCI_H
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#define SORTIX_PCI_H
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namespace Sortix {
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typedef struct
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{
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uint16_t deviceid;
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uint16_t vendorid;
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} pciid_t;
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typedef struct
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{
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uint8_t classid;
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uint8_t subclassid;
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uint8_t progif;
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uint8_t revid;
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} pcitype_t;
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// memset(&pcifind, 255, sizeof(pcifind)) and fill out rest.
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typedef struct
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{
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uint16_t deviceid;
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uint16_t vendorid;
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uint8_t classid;
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uint8_t subclassid;
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uint8_t progif;
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uint8_t revid;
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} pcifind_t;
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namespace PCI {
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void Init();
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uint32_t MakeDevAddr(uint8_t bus, uint8_t slot, uint8_t func);
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void SplitDevAddr(uint32_t devaddr, uint8_t* vals /* bus, slot, func */);
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uint8_t Read8(uint32_t devaddr, uint8_t off); // Host endian
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uint16_t Read16(uint32_t devaddr, uint8_t off); // Host endian
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uint32_t Read32(uint32_t devaddr, uint8_t off); // Host endian
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uint32_t ReadRaw32(uint32_t devaddr, uint8_t off); // PCI endian
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void Write32(uint32_t devaddr, uint8_t off, uint32_t val); // Host endian
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void WriteRaw32(uint32_t devaddr, uint8_t off, uint32_t val); // PCI endian
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pciid_t GetDeviceId(uint32_t devaddr);
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pcitype_t GetDeviceType(uint32_t devaddr);
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uint32_t SearchForDevice(pcifind_t pcifind);
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addr_t ParseDevBar0(uint32_t devaddr);
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} // namespace PCI
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} // namespace Sortix
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#endif
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@ -27,6 +27,7 @@
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#include <sortix/kernel/kthread.h>
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#include <sortix/kernel/refcount.h>
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#include <sortix/kernel/textbuffer.h>
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#include <sortix/kernel/pci.h>
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#include <libmaxsi/memory.h>
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#include <libmaxsi/string.h>
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#include <libmaxsi/format.h>
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@ -42,7 +43,7 @@
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#include "process.h"
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#include "scheduler.h"
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#include "syscall.h"
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#include "pci.h"
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#include "ata.h"
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#include "com.h"
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#include "uart.h"
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#include "vgatextbuffer.h"
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@ -218,6 +219,9 @@ extern "C" void KernelInit(unsigned long magic, multiboot_info_t* bootinfo)
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// Search for PCI devices and load their drivers.
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PCI::Init();
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// Initialize ATA devices.
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ATA::Init();
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// Alright, now the system's drivers are loaded and initialized. It is
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// time to load the initial user-space programs and start execution of
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// the actual operating system.
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431
sortix/pci.cpp
431
sortix/pci.cpp
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@ -1,6 +1,6 @@
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/******************************************************************************
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/*******************************************************************************
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COPYRIGHT(C) JONAS 'SORTIE' TERMANSEN 2011.
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Copyright(C) Jonas 'Sortie' Termansen 2011, 2012.
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This file is part of Sortix.
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@ -14,283 +14,180 @@
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along
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with Sortix. If not, see <http://www.gnu.org/licenses/>.
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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pci.h
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Handles basic PCI bus stuff.
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pci.cpp
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Functions for handling PCI devices.
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******************************************************************************/
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*******************************************************************************/
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#include <sortix/kernel/platform.h>
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#include "cpu.h"
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#include <libmaxsi/error.h>
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#include "pci.h"
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#include <sortix/kernel/log.h>
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#include "ata.h"
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#include <sortix/kernel/endian.h>
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#include <sortix/kernel/pci.h>
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#include "cpu.h" // TODO: Put this in some <sortix/kernel/cpu.h>
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using namespace Maxsi;
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// TODO: Verify that the endian conversions in this file actually works. I have
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// a sneaking suspicion that they won't work on non-little endian platforms.
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namespace Sortix
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namespace Sortix {
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namespace PCI {
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const uint16_t CONFIG_ADDRESS = 0xCF8;
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const uint16_t CONFIG_DATA = 0xCFC;
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uint32_t MakeDevAddr(uint8_t bus, uint8_t slot, uint8_t func)
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{
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namespace PCI
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//ASSERT(bus < 1UL<<8UL); // bus is 8 bit anyways.
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ASSERT(slot < 1UL<<5UL);
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ASSERT(func < 1UL<<3UL);
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return func << 8U | slot << 11U | bus << 16U | 1 << 31U;
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}
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void SplitDevAddr(uint32_t devaddr, uint8_t* vals /* bus, slot, func */)
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{
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vals[0] = devaddr >> 16U & ((1UL<<8UL)-1);
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vals[1] = devaddr >> 11U & ((1UL<<3UL)-1);
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vals[2] = devaddr >> 8U & ((1UL<<5UL)-1);
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}
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uint32_t ReadRaw32(uint32_t devaddr, uint8_t off)
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{
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CPU::OutPortL(CONFIG_ADDRESS, devaddr + off);
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return CPU::InPortL(CONFIG_DATA);
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}
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void WriteRaw32(uint32_t devaddr, uint8_t off, uint32_t val)
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{
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CPU::OutPortL(CONFIG_ADDRESS, devaddr + off);
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CPU::OutPortL(CONFIG_DATA, val);
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}
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uint32_t Read32(uint32_t devaddr, uint8_t off)
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{
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return LittleToHost(ReadRaw32(devaddr, off));
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}
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void Write32(uint32_t devaddr, uint8_t off, uint32_t val)
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{
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WriteRaw32(devaddr, off, HostToLittle(val));
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}
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uint16_t Read16(uint32_t devaddr, uint8_t off)
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{
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ASSERT((off & 0x1) == 0);
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uint8_t alignedoff = off & ~0x3;
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union { uint16_t val16[2]; uint32_t val32; };
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val32 = ReadRaw32(devaddr, alignedoff);
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uint16_t ret = off & 0x2 ? val16[0] : val16[1];
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return LittleToHost(ret);
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}
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uint8_t Read8(uint32_t devaddr, uint8_t off)
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{
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uint8_t alignedoff = off & ~0x1;
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union { uint8_t val8[2]; uint32_t val16; };
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val16 = HostToLittle(Read16(devaddr, alignedoff));
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uint8_t ret = off & 0x1 ? val8[0] : val8[1];
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return ret;
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}
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uint32_t CheckDevice(uint8_t bus, uint8_t slot, uint8_t func)
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{
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return Read32(MakeDevAddr(bus, slot, func), 0x0);
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}
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pciid_t GetDeviceId(uint32_t devaddr)
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{
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pciid_t ret;
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ret.deviceid = Read16(devaddr, 0x00);
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ret.vendorid = Read16(devaddr, 0x02);
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return ret;
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}
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pcitype_t GetDeviceType(uint32_t devaddr)
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{
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pcitype_t ret;
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ret.classid = Read8(devaddr, 0x08);
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ret.subclassid = Read8(devaddr, 0x09);
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ret.progif = Read8(devaddr, 0x0A);
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ret.revid = Read8(devaddr, 0x0B);
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return ret;
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}
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static bool MatchesSearchCriteria(uint32_t devaddr, pcifind_t pcifind)
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{
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pciid_t id = GetDeviceId(devaddr);
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if ( id.vendorid == 0xFFFF && id.deviceid == 0xFFFF )
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return false;
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pcitype_t type = GetDeviceType(devaddr);
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if ( pcifind.vendorid != 0xFFFF && id.vendorid != pcifind.vendorid )
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return false;
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if ( pcifind.deviceid != 0xFFFF && id.deviceid != pcifind.deviceid )
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return false;
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if ( pcifind.classid != 0xFF && type.classid != pcifind.classid )
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return false;
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if ( pcifind.subclassid != 0xFF && type.subclassid != pcifind.subclassid )
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return false;
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if ( pcifind.progif != 0xFF && type.progif != pcifind.progif )
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return false;
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if ( pcifind.revid != 0xFF && type.revid != pcifind.revid )
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return false;
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return true;
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}
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static uint32_t SearchForDeviceOnBus(uint8_t bus, pcifind_t pcifind)
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{
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for ( unsigned slot = 0; slot < 32; slot++ )
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{
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const uint16_t Config_Address = 0xCF8;
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const uint16_t Config_Data = 0xCFC;
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uint32_t SwapBytes(uint32_t I)
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unsigned numfuncs = 1;
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for ( unsigned func = 0; func < numfuncs; func++ )
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{
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return (I >> 24) | ((I >> 8) & 0x0000FF00) | ((I << 8) & 0x00FF0000) | (I << 24);
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uint32_t devaddr = MakeDevAddr(bus, slot, func);
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if ( MatchesSearchCriteria(devaddr, pcifind) )
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return devaddr;
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uint8_t header = Read8(devaddr, 0x0D); // Secondary Bus Number.
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if ( header & 0x80 ) // Multi function device.
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numfuncs = 8;
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if ( (header & 0x7F) == 0x01 ) // PCI to PCI bus.
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{
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uint8_t subbusid = Read8(devaddr, 0x1A);
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uint32_t recret = SearchForDeviceOnBus(subbusid, pcifind);
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if ( recret )
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return recret;
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}
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}
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}
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return 0;
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}
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const char* ToDeviceDesc(uint32_t ProductInfo, uint32_t DeviceType)
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{
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uint32_t Class = (DeviceType) >> 24;
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uint32_t SubClass = (DeviceType >> 16) & 0xFF;
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uint32_t ProgIF = (DeviceType >> 8) & 0xFF;
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uint32_t RevisionID = (DeviceType) & 0xFF;
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uint32_t SearchForDevice(pcifind_t pcifind)
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{
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// Search on bus 0 and recurse on other detected busses.
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return SearchForDeviceOnBus(0, pcifind);
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}
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if ( Class == 0x00 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Any device except for VGA-Compatible devices"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "VGA-Compatible Device"; }
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}
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if ( Class == 0x01 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "SCSI Bus Controller"; }
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if ( SubClass == 0x01 ) { return "IDE Controller"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Floppy Disk Controller"; }
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if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "IPI Bus Controller"; }
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if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "RAID Controller"; }
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if ( SubClass == 0x05 && ProgIF == 0x20 ) { return "ATA Controller (Single DMA)"; }
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if ( SubClass == 0x05 && ProgIF == 0x30 ) { return "ATA Controller (Chained DMA)"; }
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if ( SubClass == 0x06 && ProgIF == 0x00 ) { return "Serial ATA (Direct Port Access)"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Mass Storage Controller"; }
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}
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if ( Class == 0x02 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Ethernet Controller"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Token Ring Controller"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "FDDI Controller"; }
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if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "ATM Controller"; }
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if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "ISDN Controller"; }
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if ( SubClass == 0x05 && ProgIF == 0x00 ) { return "WorldFip Controller"; }
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if ( SubClass == 0x05 && ProgIF == 0x00 ) { return "ATA Controller (Chained DMA)"; }
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if ( SubClass == 0x06 ) { return "PICMG 2.14 Multi Computing"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Network Controller"; }
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}
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if ( Class == 0x03 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "VGA-Compatible Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x01 ) { return "8512-Compatible Controller"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "XGA Controller"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "3D Controller (Not VGA-Compatible)"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Display Controller"; }
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}
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if ( Class == 0x04 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Video Device"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Audio Device"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Computer Telephony Device"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Multimedia Device"; }
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}
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if ( Class == 0x05 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "RAM Controller"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Flash Controller"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Memory Controller"; }
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}
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if ( Class == 0x06 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Host Bridge"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "ISA Bridge"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "EISA Bridge"; }
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if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "MCA Bridge"; }
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if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "PCI-to-PCI Bridge"; }
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if ( SubClass == 0x04 && ProgIF == 0x01 ) { return "PCI-to-PCI Bridge (Subtractive Decode)"; }
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if ( SubClass == 0x05 && ProgIF == 0x00 ) { return "PCMCIA Bridge"; }
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if ( SubClass == 0x06 && ProgIF == 0x00 ) { return "NuBus Bridge"; }
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if ( SubClass == 0x07 && ProgIF == 0x00 ) { return "CardBus Bridge"; }
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if ( SubClass == 0x08 ) { return "RACEway Bridge"; }
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if ( SubClass == 0x09 && ProgIF == 0x40 ) { return "PCI-to-PCI Bridge (Semi-Transparent, Primary)"; }
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if ( SubClass == 0x09 && ProgIF == 0x80 ) { return "PCI-to-PCI Bridge (Semi-Transparent, Secondary)"; }
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if ( SubClass == 0x0A && ProgIF == 0x00 ) { return "InfiniBrand-to-PCI Host Bridge"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Bridge Device"; }
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}
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if ( Class == 0x07 )
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{
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if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Generic XT-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x01 ) { return "16450-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x02 ) { return "16550-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x03 ) { return "16650-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x04 ) { return "16750-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x05 ) { return "16850-Compatible Serial Controller"; }
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if ( SubClass == 0x00 && ProgIF == 0x06 ) { return "16950-Compatible Serial Controller"; }
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if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Parallel Port"; }
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if ( SubClass == 0x01 && ProgIF == 0x01 ) { return "Bi-Directional Parallel Port"; }
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if ( SubClass == 0x01 && ProgIF == 0x02 ) { return "ECP 1.X Compliant Parallel Port"; }
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if ( SubClass == 0x01 && ProgIF == 0x03 ) { return "IEEE 1284 Controller"; }
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if ( SubClass == 0x01 && ProgIF == 0xFE ) { return "IEEE 1284 Target Device"; }
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if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Multiport Serial Controller"; }
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if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "Generic Modem"; }
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if ( SubClass == 0x03 && ProgIF == 0x01 ) { return "Hayes Compatible Modem (16450-Compatible Interface)"; }
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if ( SubClass == 0x03 && ProgIF == 0x02 ) { return "Hayes Compatible Modem (16550-Compatible Interface)"; }
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if ( SubClass == 0x03 && ProgIF == 0x03 ) { return "Hayes Compatible Modem (16650-Compatible Interface)"; }
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if ( SubClass == 0x03 && ProgIF == 0x04 ) { return "Hayes Compatible Modem (16750-Compatible Interface)"; }
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if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "IEEE 488.1/2 (GPIB) Controller"; }
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if ( SubClass == 0x05 && ProgIF == 0x00 ) { return "Smart Card"; }
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if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Communications Device"; }
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}
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if ( Class == 0x08 )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Generic 8259 PIC"; }
|
||||
if ( SubClass == 0x00 && ProgIF == 0x01 ) { return "ISA PIC"; }
|
||||
if ( SubClass == 0x00 && ProgIF == 0x02 ) { return "EISA PIC"; }
|
||||
if ( SubClass == 0x00 && ProgIF == 0x10 ) { return "I/O APIC Interrupt Controller"; }
|
||||
if ( SubClass == 0x00 && ProgIF == 0x20 ) { return "I/O(x) APIC Interrupt Controller"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Generic 8237 DMA Controller"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x01 ) { return "ISA DMA Controller"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x02 ) { return "EISA DMA Controller"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Generic 8254 System Timer"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x01 ) { return "ISA System Timer"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x02 ) { return "EISA System Timer"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "Generic RTC Controller"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x01 ) { return "ISA RTC Controller"; }
|
||||
if ( SubClass == 0x04 && ProgIF == 0x01 ) { return "Generic PCI Hot-Plug Controller"; }
|
||||
if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other System Peripheral"; }
|
||||
}
|
||||
if ( Class == 0x09 )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Keyboard Controller"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Digitizer"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Mouse Controller"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "Scanner Controller"; }
|
||||
if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "Gameport Controller (Generic)"; }
|
||||
if ( SubClass == 0x04 && ProgIF == 0x10 ) { return "Gameport Controller (Legacy)"; }
|
||||
if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Input Controller"; }
|
||||
}
|
||||
if ( Class == 0x0A )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Generic Docking Station"; }
|
||||
if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Docking Station"; }
|
||||
}
|
||||
if ( Class == 0x0B )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "386 Processor"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "486 Processor"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Pentium Processor"; }
|
||||
if ( SubClass == 0x10 && ProgIF == 0x00 ) { return "Alpha Processor"; }
|
||||
if ( SubClass == 0x20 && ProgIF == 0x00 ) { return "PowerPC Processor"; }
|
||||
if ( SubClass == 0x30 && ProgIF == 0x00 ) { return "MIPS Processor"; }
|
||||
if ( SubClass == 0x40 && ProgIF == 0x00 ) { return "Co-Processor"; }
|
||||
}
|
||||
if ( Class == 0x0C )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "IEEE 1394 Controller (FireWire)"; }
|
||||
if ( SubClass == 0x00 && ProgIF == 0x10 ) { return "IEEE 1394 Controller (1394 OpenHCI Spec)"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "ACCESS.bus"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "SSA"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "USB (Universal Host Controller Spec)"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x10 ) { return "USB (Open Host Controller Spec)"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x20 ) { return "USB2 Host Controller (Intel Enhanced Host Controller Interface)"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x80 ) { return "USB"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0xFE ) { return "USB (Not Host Controller)"; }
|
||||
if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "Fibre Channel"; }
|
||||
if ( SubClass == 0x05 && ProgIF == 0x00 ) { return "SMBus"; }
|
||||
if ( SubClass == 0x06 && ProgIF == 0x00 ) { return "InfiniBand"; }
|
||||
if ( SubClass == 0x07 && ProgIF == 0x00 ) { return "IPMI SMIC Interface"; }
|
||||
if ( SubClass == 0x07 && ProgIF == 0x01 ) { return "IPMI Kybd Controller Style Interface"; }
|
||||
if ( SubClass == 0x07 && ProgIF == 0x02 ) { return "IPMI Block Transfer Interface"; }
|
||||
if ( SubClass == 0x08 && ProgIF == 0x02 ) { return "SERCOS Interface Standard (IEC 61491)"; }
|
||||
if ( SubClass == 0x09 && ProgIF == 0x00 ) { return "CANbus"; }
|
||||
}
|
||||
if ( Class == 0x0E )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Message FIFO"; }
|
||||
if ( SubClass == 0x00 ) { return "I20 Architecture"; }
|
||||
}
|
||||
if ( Class == 0x0F )
|
||||
{
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "TV Controller"; }
|
||||
if ( SubClass == 0x02 && ProgIF == 0x00 ) { return "Audio Controller"; }
|
||||
if ( SubClass == 0x03 && ProgIF == 0x00 ) { return "Voice Controller"; }
|
||||
if ( SubClass == 0x04 && ProgIF == 0x00 ) { return "Data Controller"; }
|
||||
}
|
||||
if ( Class == 0x10 )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "Network and Computing Encryption/Decryption"; }
|
||||
if ( SubClass == 0x10 && ProgIF == 0x00 ) { return "Entertainment Encryption/Decryption"; }
|
||||
if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Encryption/Decryption"; }
|
||||
}
|
||||
if ( Class == 0x11 )
|
||||
{
|
||||
if ( SubClass == 0x00 && ProgIF == 0x00 ) { return "DPIO Modules"; }
|
||||
if ( SubClass == 0x01 && ProgIF == 0x00 ) { return "Performance Counters"; }
|
||||
if ( SubClass == 0x10 && ProgIF == 0x00 ) { return "Communications Syncrhonization Plus Time and Frequency Test/Measurment"; }
|
||||
if ( SubClass == 0x20 && ProgIF == 0x00 ) { return "Management Card"; }
|
||||
if ( SubClass == 0x80 && ProgIF == 0x00 ) { return "Other Data Acquisition/Signal Processing Controller"; }
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void Init()
|
||||
{
|
||||
ATA::Init();
|
||||
#if 0
|
||||
Log::Print("PCI Devices: ");
|
||||
|
||||
for ( nat Bus = 0; Bus < 256; Bus++ )
|
||||
{
|
||||
for ( nat Slot = 0; Slot < 32; Slot++ )
|
||||
{
|
||||
for ( nat Function = 0; Function < 8; Function++ )
|
||||
{
|
||||
uint32_t ProductInfo = CheckDevice(Bus, Slot, Function);
|
||||
|
||||
if ( ProductInfo == 0xFFFFFFFF ) { continue; }
|
||||
|
||||
uint32_t DeviceType = ReadLong(Bus, Slot, Function, 0x08);
|
||||
|
||||
const char* DeviceDesc = ToDeviceDesc(ProductInfo, DeviceType);
|
||||
|
||||
if ( DeviceDesc != NULL )
|
||||
{
|
||||
Log::PrintF("%s, ", DeviceDesc);
|
||||
}
|
||||
else
|
||||
{
|
||||
Log::PrintF("Unknown PCI Device @ %x:%x.%x (ProductInfo=0x%x, DeviceType=0x%x), ", Bus, Slot, Function, ProductInfo, DeviceType);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Log::Print("\b\b\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t ReadLong(uint8_t Bus, uint8_t Slot, uint8_t Function, uint8_t Offset)
|
||||
{
|
||||
unsigned long LBus = (unsigned long) Bus;
|
||||
unsigned long LSlot = (unsigned long) Slot;
|
||||
unsigned long LFunc = (unsigned long) Function;
|
||||
|
||||
// create configuration address.
|
||||
unsigned long Address = (unsigned long) ( (LBus << 16) | (LSlot << 11) | (LFunc << 8) | (Offset & 0xFC) | ((uint32_t) 0x80000000));
|
||||
|
||||
// Write out the address.
|
||||
CPU::OutPortL(Config_Address, Address);
|
||||
|
||||
// Read in the data.
|
||||
return CPU::InPortL(Config_Data);
|
||||
|
||||
}
|
||||
|
||||
uint32_t CheckDevice(uint8_t Bus, uint8_t Slot, uint8_t Function)
|
||||
{
|
||||
return ReadLong(Bus, Slot, Function, 0);
|
||||
}
|
||||
// TODO: This is just a hack but will do for now.
|
||||
addr_t ParseDevBar0(uint32_t devaddr)
|
||||
{
|
||||
uint32_t bar0 = Read32(devaddr, 0x10);
|
||||
if ( bar0 & 0x1 ) // IO Space
|
||||
return bar0 & ~0x7UL;
|
||||
else // Memory Space
|
||||
{
|
||||
//uint32_t type = bar0 >> 1 & 0x3;
|
||||
//uint32_t prefetchable = bar0 >> 3 & 0x1;
|
||||
//if ( type == 0x01 )
|
||||
// // TODO: Support 16-bit addresses here.
|
||||
//if ( type == 0x02 )
|
||||
// // TODO: Support 64-bit addresses here.
|
||||
return bar0 & ~0xFUL;
|
||||
}
|
||||
}
|
||||
|
||||
void Init()
|
||||
{
|
||||
}
|
||||
|
||||
} // namespace PCI
|
||||
} // namespace Sortix
|
||||
|
|
|
|||
39
sortix/pci.h
39
sortix/pci.h
|
|
@ -1,39 +0,0 @@
|
|||
/******************************************************************************
|
||||
|
||||
COPYRIGHT(C) JONAS 'SORTIE' TERMANSEN 2011.
|
||||
|
||||
This file is part of Sortix.
|
||||
|
||||
Sortix is free software: you can redistribute it and/or modify it under the
|
||||
terms of the GNU General Public License as published by the Free Software
|
||||
Foundation, either version 3 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
|
||||
FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
|
||||
details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with Sortix. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
pci.h
|
||||
Handles basic PCI bus stuff.
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SORTIX_PCI_H
|
||||
#define SORTIX_PCI_H
|
||||
|
||||
namespace Sortix
|
||||
{
|
||||
namespace PCI
|
||||
{
|
||||
void Init();
|
||||
uint32_t ReadLong(uint8_t Bus, uint8_t Slot, uint8_t Function, uint8_t Offset);
|
||||
uint32_t CheckDevice(uint8_t Bus, uint8_t Slot, uint8_t Function = 0);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue