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Update kernel/uart.{cpp,h} to current coding conventions.

This commit is contained in:
Jonas 'Sortie' Termansen 2014-01-04 02:34:16 +01:00
parent c3f1550bba
commit 7a6b222e07
2 changed files with 152 additions and 163 deletions
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143
kernel/uart.cpp
View File

@ -22,17 +22,19 @@
*******************************************************************************/ *******************************************************************************/
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <sortix/kernel/cpu.h> #include <sortix/kernel/cpu.h>
#include <sortix/kernel/kernel.h> #include <sortix/kernel/kernel.h>
#include <string.h>
#include "vga.h" #include "vga.h"
#include "uart.h" #include "uart.h"
namespace Sortix namespace Sortix {
{ namespace UART {
namespace UART
{
const unsigned TXR = 0; // Transmit register const unsigned TXR = 0; // Transmit register
const unsigned RXR = 0; // Receive register const unsigned RXR = 0; // Receive register
const unsigned IER = 1; // Interrupt Enable const unsigned IER = 1; // Interrupt Enable
@ -42,10 +44,10 @@ namespace Sortix
const unsigned MCR = 4; // Modem control const unsigned MCR = 4; // Modem control
const unsigned LSR = 5; // Line Status const unsigned LSR = 5; // Line Status
const unsigned MSR = 6; // Modem Status const unsigned MSR = 6; // Modem Status
const unsigned DLL = 0; // Divisor Latch Low const unsigned DLL = 0; // divisor Latch Low
const unsigned DLM = 1; // Divisor latch High const unsigned DLM = 1; // divisor latch High
const unsigned LCR_DLAB = 0x80; // Divisor latch access bit const unsigned LCR_DLAB = 0x80; // divisor latch access bit
const unsigned LCR_SBC = 0x40; // Set break control const unsigned LCR_SBC = 0x40; // Set break control
const unsigned LCR_SPAR = 0x20; // Stick parity (?) const unsigned LCR_SPAR = 0x20; // Stick parity (?)
const unsigned LCR_EPAR = 0x10; // Even parity select const unsigned LCR_EPAR = 0x10; // Even parity select
@ -60,126 +62,113 @@ namespace Sortix
const unsigned LSR_THRE = 0x20; // Transmit-hold-register empty const unsigned LSR_THRE = 0x20; // Transmit-hold-register empty
const unsigned LSR_READY = 0x1; const unsigned LSR_READY = 0x1;
const unsigned Port = 0x3f8;
const unsigned BASE_BAUD = 1843200 / 16; const unsigned BASE_BAUD = 1843200 / 16;
const unsigned BOTH_EMPTY = LSR_TEMT | LSR_THRE; const unsigned BOTH_EMPTY = LSR_TEMT | LSR_THRE;
unsigned ProbeBaud(unsigned Port) unsigned ProbeBaud(unsigned port)
{ {
uint8_t lcr = CPU::InPortB(Port + LCR); uint8_t lcr = CPU::InPortB(port + LCR);
CPU::OutPortB(Port + LCR, lcr | LCR_DLAB); CPU::OutPortB(port + LCR, lcr | LCR_DLAB);
uint8_t dll = CPU::InPortB(Port + DLL); uint8_t dll = CPU::InPortB(port + DLL);
uint8_t dlm = CPU::InPortB(Port + DLM); uint8_t dlm = CPU::InPortB(port + DLM);
CPU::OutPortB(Port + LCR, lcr); CPU::OutPortB(port + LCR, lcr);
unsigned quot = (dlm << 8) | dll; unsigned quot = dlm << 8 | dll;
return BASE_BAUD / quot; return BASE_BAUD / quot;
} }
void WaitForEmptyBuffers(unsigned Port) void WaitForEmptyBuffers(unsigned port)
{ {
while ( true ) while ( (CPU::InPortB(port + LSR) & BOTH_EMPTY) != BOTH_EMPTY );
{
unsigned Status = CPU::InPortB(Port + LSR);
if ( (Status & BOTH_EMPTY) == BOTH_EMPTY )
{
return;
}
}
} }
unsigned Baud; const unsigned PORT = 0x3F8;
void Init() void Init()
{ {
Baud = ProbeBaud(Port); unsigned baud = ProbeBaud(PORT);
CPU::OutPortB(Port + LCR, 0x3); // 8n1 CPU::OutPortB(PORT + LCR, 0x3); // 8n1
CPU::OutPortB(Port + IER, 0); // No interrupt CPU::OutPortB(PORT + IER, 0); // No interrupt
CPU::OutPortB(Port + FCR, 0); // No FIFO CPU::OutPortB(PORT + FCR, 0); // No FIFO
CPU::OutPortB(Port + MCR, 0x3); // DTR + RTS CPU::OutPortB(PORT + MCR, 0x3); // DTR + RTS
unsigned Divisor = 115200 / Baud; unsigned divisor = 115200 / baud;
uint8_t C = CPU::InPortB(Port + LCR); uint8_t c = CPU::InPortB(PORT + LCR);
CPU::OutPortB(Port + LCR, C | LCR_DLAB); CPU::OutPortB(PORT + LCR, c | LCR_DLAB);
CPU::OutPortB(Port + DLL, Divisor & 0xFF); CPU::OutPortB(PORT + DLL, divisor >> 0 & 0xFF);
CPU::OutPortB(Port + DLM, (Divisor >> 8) & 0xFF); CPU::OutPortB(PORT + DLM, divisor >> 8 & 0xFF);
CPU::OutPortB(Port + LCR, C & ~LCR_DLAB); CPU::OutPortB(PORT + LCR, c & ~LCR_DLAB);
} }
void Read(uint8_t* Buffer, size_t Size) void Read(uint8_t* buffer, size_t size)
{ {
// Save the IER and disable interrupts. // Save the IER and disable interrupts.
unsigned ier = CPU::InPortB(Port + IER); unsigned ier = CPU::InPortB(PORT + IER);
CPU::OutPortB(Port + IER, 0); CPU::OutPortB(PORT + IER, 0);
for ( size_t I = 0; I < Size; I++ ) for ( size_t i = 0; i < size; i++ )
{ {
while ( ! ( CPU::InPortB(Port + LSR) & LSR_READY ) ) { } while ( !(CPU::InPortB(PORT + LSR) & LSR_READY) );
buffer[i] = CPU::InPortB(PORT);
Buffer[I] = CPU::InPortB(Port);
} }
// Wait for transmitter to become empty and restore the IER. // Wait for transmitter to become empty and restore the IER.
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(Port + IER, ier); CPU::OutPortB(PORT + IER, ier);
} }
void Write(const void* B, size_t Size) void Write(const void* b, size_t size)
{ {
const uint8_t* Buffer = (const uint8_t*) B; const uint8_t* buffer = (const uint8_t*) b;
// Save the IER and disable interrupts. // Save the IER and disable interrupts.
unsigned ier = CPU::InPortB(Port + IER); unsigned ier = CPU::InPortB(PORT + IER);
CPU::OutPortB(Port + IER, 0); CPU::OutPortB(PORT + IER, 0);
for ( size_t I = 0; I < Size; I++ ) for ( size_t i = 0; i < size; i++ )
{ {
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(PORT, buffer[i]);
CPU::OutPortB(Port, Buffer[I]);
} }
// Wait for transmitter to become empty and restore the IER. // Wait for transmitter to become empty and restore the IER.
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(Port + IER, ier); CPU::OutPortB(PORT + IER, ier);
} }
void WriteChar(char C) void WriteChar(char c)
{ {
// Save the IER and disable interrupts. // Save the IER and disable interrupts.
unsigned ier = CPU::InPortB(Port + IER); unsigned ier = CPU::InPortB(PORT + IER);
CPU::OutPortB(Port + IER, 0); CPU::OutPortB(PORT + IER, 0);
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(Port, C); CPU::OutPortB(PORT, c);
// Wait for transmitter to become empty and restore the IER. // Wait for transmitter to become empty and restore the IER.
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(Port + IER, ier); CPU::OutPortB(PORT + IER, ier);
} }
int TryPopChar() int TryPopChar()
{ {
// Save the IER and disable interrupts. // Save the IER and disable interrupts.
unsigned ier = CPU::InPortB(Port + IER); unsigned ier = CPU::InPortB(PORT + IER);
CPU::OutPortB(Port + IER, 0); CPU::OutPortB(PORT + IER, 0);
int Result = -1; int result = -1;
if ( CPU::InPortB(Port + LSR) & LSR_READY ) if ( CPU::InPortB(PORT + LSR) & LSR_READY )
{ result = CPU::InPortB(PORT);
Result = CPU::InPortB(Port);
}
// Wait for transmitter to become empty and restore the IER. // Wait for transmitter to become empty and restore the IER.
WaitForEmptyBuffers(Port); WaitForEmptyBuffers(PORT);
CPU::OutPortB(Port + IER, ier); CPU::OutPortB(PORT + IER, ier);
return Result; return result;
}
}
} }
} // namespace UART
} // namespace Sortix

18
kernel/uart.h
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@ -25,16 +25,16 @@
#ifndef SORTIX_UART_H #ifndef SORTIX_UART_H
#define SORTIX_UART_H #define SORTIX_UART_H
namespace Sortix namespace Sortix {
{ namespace UART {
namespace UART
{
void Init(); void Init();
void Read(uint8_t* Buffer, size_t Size); void Read(uint8_t* buffer, size_t size);
void Write(const void* Buffer, size_t Size); void Write(const void* buffer, size_t size);
void WriteChar(char C); void WriteChar(char c);
int TryPopChar(); int TryPopChar();
}
} } // namespace UART
} // namespace Sortix
#endif #endif