mirror of
https://gitlab.com/sortix/sortix.git
synced 2023-02-13 20:55:38 -05:00
239 lines
5.9 KiB
ArmAsm
239 lines
5.9 KiB
ArmAsm
/*
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* Copyright (c) 2011, 2014, 2015, 2016, 2018 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* x64/boot.S
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* Bootstraps the kernel and passes over control from the boot-loader to the
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* kernel main function. It also jumps into long mode!
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*/
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.section .text.unlikely
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# Multiboot header.
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.align 4
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.long 0x1BADB002 # Magic.
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.long 0x00000007 # Flags.
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.long -(0x1BADB002 + 0x00000007) # Checksum
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.skip 32-12
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.long 0 # Mode
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.long 0 # Width
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.long 0 # Height
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.long 0 # Depth
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.section .bss, "aw", @nobits
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.align 4096
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bootpml4:
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.skip 4096
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bootpml3:
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.skip 4096
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bootpml2:
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.skip 4096
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bootpml1_a:
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.skip 4096
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bootpml1_b:
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.skip 4096
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fracpml3:
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.skip 4096
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fracpml2:
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.skip 4096
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fracpml1:
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.skip 4096
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forkpml2:
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.skip 4096
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forkpml1:
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.skip 4096
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physpml3:
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.skip 4096
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physpml2:
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.skip 4096
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physpml1:
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.skip 4096
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physpml0:
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.skip 4096
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nullpage: .global nullpage
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.skip 4096
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.section .text
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.global _start
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.global __start
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.type _start, @function
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.type __start, @function
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.code32
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_start:
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__start:
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# Clear the direction flag.
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cld
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# Initialize the stack pointer. The magic value is from kernel.cpp.
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movl $(stack + 65536), %esp # 64 KiB, see kernel.cpp (See below also)
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# Finish installing the kernel stack into the Task Switch Segment.
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movl %esp, tss + 4
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movl $0, tss + 8
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# Finish installing the Task Switch Segment into the Global Descriptor Table.
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movl $tss, %ecx
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movw %cx, gdt + 0x28 + 2
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shrl $16, %ecx
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movb %cl, gdt + 0x28 + 4
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shrl $8, %ecx
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movb %cl, gdt + 0x28 + 7
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movl $0, gdt + 0x28 + 8
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# We got our multiboot information in various registers.
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pushl $0
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pushl %eax # Multiboot magic value.
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pushl $0
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pushl %ebx # Multiboot information structure pointer.
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movl $bootpml4, %edi
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movl %edi, %cr3
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# Page-Map Level 4.
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movl $(bootpml3 + 0x207), bootpml4 + 0 * 8
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# Page Directory Pointer Table.
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movl $(bootpml2 + 0x207), bootpml3 + 0 * 8
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# Page Directory (no user-space access here).
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movl $(bootpml1_a + 0x003), bootpml2 + 0 * 8
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movl $(bootpml1_b + 0x003), bootpml2 + 1 * 8
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# Page Table (identity map the first 4 MiB, except NULL).
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# TODO: This is insecure as it doesn't restrict write & execute access to
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# the code kernel code & variables appropriately.
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movl $(bootpml1_a + 8), %edi
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movl $0x1003, %esi
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movl $1023, %ecx
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1:
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movl %esi, (%edi)
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addl $0x1000, %esi
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addl $8, %edi
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loop 1b
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# Map the null page.
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movl $nullpage, %edi
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shrl $12, %edi
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movl $0x0003, bootpml1_a(, %edi, 8)
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# Fractal mapping.
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movl $(bootpml4 + 0x003), bootpml4 + 511 * 8
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movl $(fracpml3 + 0x203), bootpml4 + 510 * 8
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movl $(bootpml4 + 0x003), fracpml3 + 511 * 8
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movl $(fracpml2 + 0x203), fracpml3 + 510 * 8
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movl $(bootpml4 + 0x003), fracpml2 + 511 * 8
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movl $(fracpml1 + 0x203), fracpml2 + 510 * 8
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movl $(bootpml4 + 0x003), fracpml1 + 511 * 8
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# Predefined room for forking address spaces.
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movl $(forkpml2 + 0x203), fracpml3 + 0 * 8
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movl $(forkpml1 + 0x203), forkpml2 + 0 * 8
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# Physical page allocator.
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movl $(physpml3 + 0x003), bootpml4 + 509 * 8
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movl $(physpml2 + 0x003), physpml3 + 0 * 8
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movl $(physpml1 + 0x003), physpml2 + 0 * 8
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movl $(physpml0 + 0x003), physpml1 + 0 * 8
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# Enable PAE.
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movl %cr4, %eax
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orl $0x20, %eax
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movl %eax, %cr4
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# Enable long mode and the No-Execute bit.
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movl $0xC0000080, %ecx
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rdmsr
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orl $0x900, %eax
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wrmsr
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# Enable paging (with write protection) and enter long mode (still 32-bit)
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movl %cr0, %eax
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orl $0x80010000, %eax
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movl %eax, %cr0
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# Load the Global Descriptor Table pointer register.
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subl $6, %esp
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movw gdt_size_minus_one, %cx
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movw %cx, 0(%esp)
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movl $gdt, %ecx
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movl %ecx, 2(%esp)
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lgdt 0(%esp)
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addl $6, %esp
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# Now use the 64-bit code segment, and we are in full 64-bit mode.
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ljmp $0x08, $2f
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.code64
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2:
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# The upper 32 bits of the general purpose registers are *undefined* after
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# switching into 64-bit mode (Intel Manual, Vol 1, 3.4.1.1 "General-Purpose
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# Registers in 64-Bit Mode"). The lower 32 bits are preserved from 32-bit
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# mode. Any registers whose value we wish to retain must have its upper 32
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# bits masked off. Assigning a register to itself in a 32-bit operation will
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# zero the upper 32 bits. The only register the below code assumes is
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# retained is the stack register (esp/rsp).
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mov %esp, %esp
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# Switch ds, es, fs, gs, ss to the kernel data segment (0x10).
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movw $0x10, %cx
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movw %cx, %ds
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movw %cx, %es
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movw %cx, %ss
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# Switch the task switch segment register to the task switch segment (0x28).
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movw $(0x28 /* TSS */ | 0x3 /* RPL */), %cx
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ltr %cx
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# Switch to the thread local fs and gs segments.
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movw $(0x20 /* DS */ | 0x3 /* RPL */), %cx
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movw %cx, %fs
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movw %cx, %gs
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# Enable the floating point unit.
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mov %cr0, %rax
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and $0xFFFD, %ax
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or $0x10, %ax
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mov %rax, %cr0
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fninit
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# Enable Streaming SIMD Extensions.
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mov %cr0, %rax
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and $0xFFFB, %ax
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or $0x2, %ax
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mov %rax, %cr0
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mov %cr4, %rax
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or $0x600, %rax
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mov %rax, %cr4
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push $0x1F80
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ldmxcsr (%rsp)
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addq $8, %rsp
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# Store a copy of the initialial floating point registers.
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fxsave fpu_initialized_regs
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# Enter the high-level kernel proper.
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pop %rsi # Multiboot information structure pointer.
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pop %rdi # Multiboot magic value.
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call KernelInit
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jmp HaltKernel
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.size _start, . - _start
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.size __start, . - __start
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.global HaltKernel
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.type HaltKernel, @function
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HaltKernel:
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cli
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hlt
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jmp HaltKernel
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.size HaltKernel, . - HaltKernel
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