mirror of
https://gitlab.com/sortix/sortix.git
synced 2023-02-13 20:55:38 -05:00
308 lines
8.7 KiB
C++
308 lines
8.7 KiB
C++
/*
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* Copyright (c) 2011, 2012, 2013, 2014, 2015, 2016 Jonas 'Sortie' Termansen.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* pci.cpp
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* Functions for handling PCI devices.
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*/
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#include <assert.h>
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#include <endian.h>
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#include <sortix/kernel/cpu.h>
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#include <sortix/kernel/interrupt.h>
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#include <sortix/kernel/ioport.h>
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#include <sortix/kernel/kernel.h>
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#include <sortix/kernel/kthread.h>
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#include <sortix/kernel/pci.h>
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namespace Sortix {
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namespace PCI {
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static kthread_mutex_t pci_lock = KTHREAD_MUTEX_INITIALIZER;
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static const uint16_t CONFIG_ADDRESS = 0xCF8;
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static const uint16_t CONFIG_DATA = 0xCFC;
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uint32_t MakeDevAddr(uint8_t bus, uint8_t slot, uint8_t func)
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{
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//assert(bus < 1UL<<8UL); // bus is 8 bit anyways.
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assert(slot < 1UL<<5UL);
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assert(func < 1UL<<3UL);
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return func << 8U | slot << 11U | bus << 16U | 1 << 31U;
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}
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void SplitDevAddr(uint32_t devaddr, uint8_t* vals /* bus, slot, func */)
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{
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vals[0] = devaddr >> 16U & ((1UL<<8UL)-1);
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vals[1] = devaddr >> 11U & ((1UL<<3UL)-1);
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vals[2] = devaddr >> 8U & ((1UL<<5UL)-1);
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}
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uint32_t ReadRaw32(uint32_t devaddr, uint8_t off)
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{
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assert((off & 0x3) == 0);
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outport32(CONFIG_ADDRESS, devaddr + off);
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return inport32(CONFIG_DATA);
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}
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void WriteRaw32(uint32_t devaddr, uint8_t off, uint32_t val)
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{
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assert((off & 0x3) == 0);
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outport32(CONFIG_ADDRESS, devaddr + off);
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outport32(CONFIG_DATA, val);
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}
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uint32_t Read32(uint32_t devaddr, uint8_t off)
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{
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return le32toh(ReadRaw32(devaddr, off));
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}
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void Write32(uint32_t devaddr, uint8_t off, uint32_t val)
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{
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WriteRaw32(devaddr, off, htole32(val));
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}
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void Write16(uint32_t devaddr, uint8_t off, uint16_t val)
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{
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assert((off & 0x1) == 0);
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uint8_t alignedoff = off & ~0x3;
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union { uint8_t val8[4]; uint32_t val32; };
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val32 = ReadRaw32(devaddr, alignedoff);
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val8[(off & 0x3) + 0] = val >> 0 & 0xFF;
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val8[(off & 0x3) + 1] = val >> 8 & 0xFF;
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WriteRaw32(devaddr, alignedoff, val32);
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}
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uint16_t Read16(uint32_t devaddr, uint8_t off)
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{
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assert((off & 0x1) == 0);
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uint8_t alignedoff = off & ~0x3;
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union { uint8_t val8[4]; uint32_t val32; };
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val32 = ReadRaw32(devaddr, alignedoff);
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return (uint16_t) val8[(off & 0x3) + 0] << 0 |
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(uint16_t) val8[(off & 0x3) + 1] << 8;
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}
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void Write8(uint32_t devaddr, uint8_t off, uint8_t val)
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{
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uint8_t alignedoff = off & ~0x3;
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union { uint8_t val8[4]; uint32_t val32; };
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val32 = ReadRaw32(devaddr, alignedoff);
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val8[(off & 0x3)] = val;
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WriteRaw32(devaddr, alignedoff, val32);
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}
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uint8_t Read8(uint32_t devaddr, uint8_t off)
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{
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uint8_t alignedoff = off & ~0x3;
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union { uint8_t val8[4]; uint32_t val32; };
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val32 = ReadRaw32(devaddr, alignedoff);
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return val8[(off & 0x3)];
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}
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uint32_t CheckDevice(uint8_t bus, uint8_t slot, uint8_t func)
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{
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return Read32(MakeDevAddr(bus, slot, func), 0x0);
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}
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pciid_t GetDeviceId(uint32_t devaddr)
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{
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pciid_t ret;
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ret.deviceid = Read16(devaddr, PCIFIELD_DEVICE_ID);
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ret.vendorid = Read16(devaddr, PCIFIELD_VENDOR_ID);
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return ret;
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}
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pcitype_t GetDeviceType(uint32_t devaddr)
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{
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pcitype_t ret;
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ret.classid = Read8(devaddr, PCIFIELD_CLASS);
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ret.subclassid = Read8(devaddr, PCIFIELD_SUBCLASS);
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ret.progif = Read8(devaddr, PCIFIELD_PROG_IF);
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ret.revid = Read8(devaddr, PCIFIELD_REVISION_ID);
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return ret;
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}
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static bool MatchesSearchCriteria(uint32_t devaddr, pcifind_t pcifind)
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{
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pciid_t id = GetDeviceId(devaddr);
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if ( id.vendorid == 0xFFFF && id.deviceid == 0xFFFF )
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return false;
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pcitype_t type = GetDeviceType(devaddr);
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if ( pcifind.vendorid != 0xFFFF && id.vendorid != pcifind.vendorid )
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return false;
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if ( pcifind.deviceid != 0xFFFF && id.deviceid != pcifind.deviceid )
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return false;
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if ( pcifind.classid != 0xFF && type.classid != pcifind.classid )
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return false;
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if ( pcifind.subclassid != 0xFF && type.subclassid != pcifind.subclassid )
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return false;
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if ( pcifind.progif != 0xFF && type.progif != pcifind.progif )
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return false;
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if ( pcifind.revid != 0xFF && type.revid != pcifind.revid )
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return false;
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return true;
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}
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// TODO: This iterates the whole PCI device tree on each call!
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static uint32_t SearchForDevicesOnBus(uint8_t bus, pcifind_t pcifind, uint32_t last = 0)
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{
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bool found_any_device = false;
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uint32_t next_device = 0;
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for ( unsigned int slot = 0; slot < 32; slot++ )
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{
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unsigned int num_functions = 1;
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for ( unsigned int function = 0; function < num_functions; function++ )
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{
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uint32_t devaddr = MakeDevAddr(bus, slot, function);
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if ( last < devaddr &&
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(!found_any_device || devaddr < next_device) &&
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MatchesSearchCriteria(devaddr, pcifind) )
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next_device = devaddr, found_any_device = true;
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uint8_t header = Read8(devaddr, PCIFIELD_HEADER_TYPE);
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if ( header & 0x80 ) // Multi function device.
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num_functions = 8;
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if ( (header & 0x7F) == 0x01 ) // PCI to PCI bus.
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{
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uint8_t subbusid = Read8(devaddr, PCIFIELD_SECONDARY_BUS_NUMBER);
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uint32_t recret = SearchForDevicesOnBus(subbusid, pcifind, last);
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if ( last < recret &&
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(!found_any_device || recret < next_device) )
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next_device = recret, found_any_device = true;
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}
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}
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}
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if ( !found_any_device )
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return 0;
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return next_device;
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}
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uint32_t SearchForDevices(pcifind_t pcifind, uint32_t last)
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{
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// Search on bus 0 and recurse on other detected busses.
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return SearchForDevicesOnBus(0, pcifind, last);
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}
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pcibar_t GetBAR(uint32_t devaddr, uint8_t bar)
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{
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ScopedLock lock(&pci_lock);
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uint32_t low = PCI::Read32(devaddr, 0x10 + 4 * (bar+0));
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pcibar_t result;
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result.addr_raw = low;
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result.size_raw = 0;
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if ( result.is_64bit() )
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{
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uint32_t high = PCI::Read32(devaddr, 0x10 + 4 * (bar+1));
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result.addr_raw |= (uint64_t) high << 32;
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), 0xFFFFFFFF);
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PCI::Write32(devaddr, 0x10 + 4 * (bar+1), 0xFFFFFFFF);
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uint32_t size_low = PCI::Read32(devaddr, 0x10 + 4 * (bar+0));
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uint32_t size_high = PCI::Read32(devaddr, 0x10 + 4 * (bar+1));
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), low);
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PCI::Write32(devaddr, 0x10 + 4 * (bar+1), high);
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result.size_raw = (uint64_t) size_high << 32 | (uint64_t) size_low << 0;
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result.size_raw = ~(result.size_raw & 0xFFFFFFFFFFFFFFF0) + 1;
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}
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else if ( result.is_32bit() )
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{
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), 0xFFFFFFFF);
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uint32_t size_low = PCI::Read32(devaddr, 0x10 + 4 * (bar+0));
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), low);
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result.size_raw = (uint64_t) size_low << 0;
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result.size_raw = ~(result.size_raw & 0xFFFFFFF0) + 1;
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result.size_raw &= 0xFFFFFFFF;
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}
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else if ( result.is_iospace() )
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{
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), 0xFFFFFFFF);
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uint32_t size_low = PCI::Read32(devaddr, 0x10 + 4 * (bar+0));
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PCI::Write32(devaddr, 0x10 + 4 * (bar+0), low);
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result.size_raw = (uint64_t) size_low << 0;
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result.size_raw = ~(result.size_raw & 0xFFFFFFFC) + 1;
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result.size_raw &= 0xFFFFFFFF;
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}
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return result;
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}
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pcibar_t GetExpansionROM(uint32_t devaddr)
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{
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const uint32_t ROM_ADDRESS_MASK = ~UINT32_C(0x7FF);
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ScopedLock lock(&pci_lock);
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uint32_t low = PCI::Read32(devaddr, 0x30);
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PCI::Write32(devaddr, 0x30, ROM_ADDRESS_MASK | low);
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uint32_t size_low = PCI::Read32(devaddr, 0x30);
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PCI::Write32(devaddr, 0x30, low);
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pcibar_t result;
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result.addr_raw = (low & ROM_ADDRESS_MASK) | PCIBAR_TYPE_32BIT;
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result.size_raw = ~(size_low & ROM_ADDRESS_MASK) + 1;
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return result;
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}
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void EnableExpansionROM(uint32_t devaddr)
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{
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ScopedLock lock(&pci_lock);
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PCI::Write32(devaddr, 0x30, PCI::Read32(devaddr, 0x30) | 0x1);
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}
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void DisableExpansionROM(uint32_t devaddr)
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{
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ScopedLock lock(&pci_lock);
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PCI::Write32(devaddr, 0x30, PCI::Read32(devaddr, 0x30) & ~UINT32_C(0x1));
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}
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bool IsExpansionROMEnabled(uint32_t devaddr)
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{
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ScopedLock lock(&pci_lock);
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return PCI::Read32(devaddr, 0x30) & 0x1;
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}
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static bool IsOkayInterruptLine(uint8_t line)
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{
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if ( line == 0 )
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return false; // Conflict with PIT.
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if ( line == 2 )
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return false; // Cascade, can't be received.
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if ( 16 <= line )
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return false; // Not in set of valid IRQs.
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return true;
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}
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uint8_t SetupInterruptLine(uint32_t devaddr)
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{
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ScopedLock lock(&pci_lock);
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uint8_t line = Read8(devaddr, PCIFIELD_INTERRUPT_LINE);
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if ( !IsOkayInterruptLine(line) )
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return 0;
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return Interrupt::IRQ0 + line;
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}
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void Init()
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{
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}
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} // namespace PCI
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} // namespace Sortix
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