mirror of
https://gitlab.com/sortix/sortix.git
synced 2023-02-13 20:55:38 -05:00
317 lines
8.9 KiB
C++
317 lines
8.9 KiB
C++
/*******************************************************************************
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Copyright(C) Jonas 'Sortie' Termansen 2011, 2012, 2014.
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This file is part of Sortix.
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Sortix is free software: you can redistribute it and/or modify it under the
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terms of the GNU General Public License as published by the Free Software
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Foundation, either version 3 of the License, or (at your option) any later
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version.
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Sortix is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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details.
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You should have received a copy of the GNU General Public License along with
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Sortix. If not, see <http://www.gnu.org/licenses/>.
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com.cpp
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Handles communication to COM serial ports.
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*******************************************************************************/
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#include <errno.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <sortix/fcntl.h>
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#include <sortix/stat.h>
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#include <sortix/kernel/descriptor.h>
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#include <sortix/kernel/inode.h>
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#include <sortix/kernel/interlock.h>
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#include <sortix/kernel/interrupt.h>
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#include <sortix/kernel/ioctx.h>
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#include <sortix/kernel/ioport.h>
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#include <sortix/kernel/kernel.h>
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#include <sortix/kernel/kthread.h>
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#include <sortix/kernel/process.h>
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#include <sortix/kernel/refcount.h>
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#include <sortix/kernel/thread.h>
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#include "com.h"
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extern "C" unsigned char nullpage[4096];
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namespace Sortix {
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namespace COM {
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static const uint16_t TXR = 0; // Transmit register
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static const uint16_t RXR = 0; // Receive register
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static const uint16_t IER = 1; // Interrupt Enable
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static const uint16_t IIR = 2; // Interrupt ID
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static const uint16_t FCR = 2; // FIFO control
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static const uint16_t LCR = 3; // Line control
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static const uint16_t MCR = 4; // Modem control
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static const uint16_t LSR = 5; // Line Status
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static const uint16_t MSR = 6; // Modem Status
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static const uint16_t SCR = 7; // Scratch Register
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static const uint16_t DLL = 0; // Divisor Latch Low
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static const uint16_t DLM = 1; // Divisor latch High
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static const uint8_t LCR_DLAB = 0x80; // Divisor latch access bit
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static const uint8_t LCR_SBC = 0x40; // Set break control
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static const uint8_t LCR_SPAR = 0x20; // Stick parity (?)
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static const uint8_t LCR_EPAR = 0x10; // Even parity select
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static const uint8_t LCR_PARITY = 0x08; // Parity Enable
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static const uint8_t LCR_STOP = 0x04; // Stop bits: 0=1 bit, 1=2 bits
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static const uint8_t LCR_WLEN5 = 0x00; // Wordlength: 5 bits
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static const uint8_t LCR_WLEN6 = 0x01; // Wordlength: 6 bits
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static const uint8_t LCR_WLEN7 = 0x02; // Wordlength: 7 bits
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static const uint8_t LCR_WLEN8 = 0x03; // Wordlength: 8 bits
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static const uint8_t LSR_TEMT = 0x40; // Transmitter empty
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static const uint8_t LSR_THRE = 0x20; // Transmit-hold-register empty
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static const uint8_t LSR_READY = 0x01; // Data received
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static const uint8_t LSR_BOTH_EMPTY = LSR_TEMT | LSR_THRE;
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static const uint8_t IIR_NO_INTERRUPT = 1 << 0;
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static const uint8_t IIR_INTERRUPT_TYPE = 1 << 1 | 1 << 2 | 1 << 3;
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static const uint8_t IIR_TIMEOUT = 1 << 2 | 1 << 3;
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static const uint8_t IIR_RECV_LINE_STATUS = 1 << 1 | 1 << 2;
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static const uint8_t IIR_RECV_DATA = 1 << 2;
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static const uint8_t IIR_SENT_DATA = 1 << 1;
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static const uint8_t IIR_MODEM_STATUS = 0;
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static const uint8_t IER_DATA = 1 << 0;
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static const uint8_t IER_SENT = 1 << 1;
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static const uint8_t IER_LINE_STATUS = 1 << 2;
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static const uint8_t IER_MODEM_STATUS = 1 << 3;
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static const uint8_t IER_SLEEP_MODE = 1 << 4;
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static const uint8_t IER_LOW_POWER = 1 << 5;
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static const unsigned BASE_BAUD = 1843200 / 16;
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static const unsigned int UART_8250 = 1;
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static const unsigned int UART_16450 = 2;
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static const unsigned int UART_16550 = 3;
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static const unsigned int UART_16550A = 4;
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static const unsigned int UART_16750 = 5;
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static const size_t NUM_COM_PORTS = 4;
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// Uses various characteristics of the UART chips to determine the hardware.
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static unsigned int HardwareProbe(uint16_t port)
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{
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// Set the value "0xE7" to the FCR to test the status of the FIFO flags.
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outport8(port + FCR, 0xE7);
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uint8_t iir = inport8(port + IIR);
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if ( iir & (1 << 6) )
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{
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if ( iir & (1 << 7) )
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return iir & (1 << 5) ? UART_16750 : UART_16550A;
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return UART_16550;
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}
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// See if the scratch register returns what we write into it. The 8520
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// doesn't do it. This is technically undefined behavior, but it is useful
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// to detect hardware versions.
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uint16_t any_value = 0x2A;
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outport8(port + SCR, any_value);
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return inport8(port + SCR) == any_value ? UART_16450 : UART_8250;
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}
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static inline void WaitForEmptyBuffers(uint16_t port)
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{
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while ( (inport8(port + LSR) & LSR_BOTH_EMPTY) != LSR_BOTH_EMPTY )
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{
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}
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}
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static inline bool IsLineReady(uint16_t port)
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{
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return inport8(port + LSR) & LSR_READY;
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}
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static inline bool CanWriteByte(uint16_t port)
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{
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return inport8(port + LSR) & LSR_THRE;
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}
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class DevCOMPort : public AbstractInode
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{
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public:
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DevCOMPort(dev_t dev, uid_t owner, gid_t group, mode_t mode, uint16_t port);
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virtual ~DevCOMPort();
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virtual int sync(ioctx_t* ctx);
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virtual ssize_t read(ioctx_t* ctx, uint8_t* buf, size_t count);
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virtual ssize_t write(ioctx_t* ctx, const uint8_t* buf, size_t count);
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private:
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kthread_mutex_t port_lock;
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uint16_t port;
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uint8_t pending_input_byte;
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bool has_pending_input_byte;
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};
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DevCOMPort::DevCOMPort(dev_t dev, uid_t owner, gid_t group, mode_t mode,
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uint16_t port)
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{
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inode_type = INODE_TYPE_STREAM;
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this->port = port;
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this->port_lock = KTHREAD_MUTEX_INITIALIZER;
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this->stat_uid = owner;
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this->stat_gid = group;
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this->type = S_IFCHR;
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this->stat_mode = (mode & S_SETABLE) | this->type;
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this->dev = dev;
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this->ino = (ino_t) this;
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this->has_pending_input_byte = false;
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}
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DevCOMPort::~DevCOMPort()
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{
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}
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int DevCOMPort::sync(ioctx_t* /*ctx*/)
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{
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ScopedLock lock(&port_lock);
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WaitForEmptyBuffers(port);
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return 0;
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}
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ssize_t DevCOMPort::read(ioctx_t* ctx, uint8_t* dest, size_t count)
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{
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ScopedLock lock(&port_lock);
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for ( size_t i = 0; i < count; i++ )
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{
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unsigned long attempt = 0;
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while ( !has_pending_input_byte && !IsLineReady(port) )
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{
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attempt++;
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if ( attempt <= 10 )
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continue;
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if ( attempt <= 15 && !(ctx->dflags & O_NONBLOCK) )
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{
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kthread_yield();
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continue;
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}
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if ( i )
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return (ssize_t) i;
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if ( ctx->dflags & O_NONBLOCK )
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return errno = EWOULDBLOCK, -1;
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if ( Signal::IsPending() )
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return errno = EINTR, -1;
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kthread_yield();
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}
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uint8_t value = has_pending_input_byte ?
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pending_input_byte :
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inport8(port + RXR);
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if ( !ctx->copy_to_dest(dest + i, &value, sizeof(value)) )
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{
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has_pending_input_byte = true;
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pending_input_byte = value;
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return i ? (ssize_t) i : -1;
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}
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has_pending_input_byte = false;
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}
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return (ssize_t) count;
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}
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ssize_t DevCOMPort::write(ioctx_t* ctx, const uint8_t* src, size_t count)
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{
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ScopedLock lock(&port_lock);
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for ( size_t i = 0; i < count; i++ )
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{
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unsigned long attempt = 0;
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while ( !CanWriteByte(port) )
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{
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attempt++;
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if ( attempt <= 10 )
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continue;
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if ( attempt <= 15 && !(ctx->dflags & O_NONBLOCK) )
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{
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kthread_yield();
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continue;
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}
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if ( i )
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return (ssize_t) i;
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if ( ctx->dflags & O_NONBLOCK )
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return errno = EWOULDBLOCK, -1;
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if ( Signal::IsPending() )
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return errno = EINTR, -1;
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}
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uint8_t value;
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if ( !ctx->copy_from_src(&value, src + i, sizeof(value)) )
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return i ? (ssize_t) i : -1;
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outport8(port + TXR, value);
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}
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return (ssize_t) count;
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}
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static Ref<DevCOMPort> com_devices[1 + NUM_COM_PORTS];
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void Init(const char* devpath, Ref<Descriptor> slashdev)
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{
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uint16_t com_ports[1 + NUM_COM_PORTS];
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unsigned int hw_version[1 + NUM_COM_PORTS];
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const uint16_t* bioscom_ports = (const uint16_t*) (nullpage + 0x400);
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for ( size_t i = 1; i <= NUM_COM_PORTS; i++ )
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{
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if ( !(com_ports[i] = bioscom_ports[i-1]) )
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continue;
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hw_version[i] = HardwareProbe(com_ports[i]);
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outport8(com_ports[i] + IER, 0x0);
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}
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(void) hw_version;
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ioctx_t ctx; SetupKernelIOCtx(&ctx);
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for ( size_t i = 1; i <= NUM_COM_PORTS; i++ )
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{
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uint16_t port = com_ports[i];
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if ( !port )
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continue;
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uint8_t interrupts = 0;
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outport8(port + FCR, 0);
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outport8(port + LCR, 0x80);
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outport8(port + DLL, 0xC);
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outport8(port + DLM, 0x0);
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outport8(port + LCR, 0x3); // 8n1
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outport8(port + MCR, 0x3); // DTR + RTS
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outport8(port + IER, interrupts);
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}
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for ( size_t i = 1; i <= NUM_COM_PORTS; i++ )
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{
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if ( !com_ports[i] )
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{
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com_devices[i] = Ref<DevCOMPort>();
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continue;
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}
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com_devices[i] = Ref<DevCOMPort>(new DevCOMPort(slashdev->dev, 0, 0, 0660, com_ports[i]));
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if ( !com_devices[i] )
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PanicF("Unable to allocate device for COM port %zu", i);
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char name[3 + sizeof(size_t) * 3];
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snprintf(name, sizeof(name), "com%zu", i);
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if ( LinkInodeInDir(&ctx, slashdev, name, com_devices[i]) != 0 )
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PanicF("Unable to link %s/%s to COM port driver.", devpath, name);
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}
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}
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} // namespace COM
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} // namespace Sortix
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